IP Library Granted Patent US 9,362,873
Granted Patent B2
US 9,362,873 · App. 14/810,853 · Granted Jun 7, 2016

Instrumentation amplifier

Inventor: Yasunari Harada (Ebina, JP)
Assignee: OLYMPUS CORPORATION
H03F3/45179H03F3/45197H03F2200/261H03F2203/45026
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Quick Facts
Patent No.
US 9,362,873
App. No.
14/810,853
Granted
Jun 7, 2016
Kind
B2
Abstract

An instrumentation amplifier includes: a first input stage configured to shift a level of a first input voltage applied to a first input terminal and to output the level-shifted voltage; a second input stage configured to shift a level of a second input voltage applied to a second input terminal and to output the level-shifted voltage; a first resistor configured to generate a differential current corresponding to a difference between the voltage output from the first input stage and the voltage output from the second input stage; a second resistor configured to convert the differential current into a first output voltage; a third resistor configured to convert the differential current into a second output voltage; a first output stage configured to output the first output voltage from a first output terminal; and a second output stage configured to output the second output voltage from a second output terminal.

Claims (28)

1. An instrumentation amplifier comprising:

a first input stage configured to shift a level of a first input voltage applied to a first input terminal and to output the level-shifted voltage;

a second input stage configured to shift a level of a second input voltage applied to a second input terminal and to output the level-shifted voltage;

a first resistor configured to generate a differential current corresponding to a difference between the voltage output from the first input stage and the voltage output from the second input stage;

a second resistor configured to convert the differential current into a first output voltage;

a third resistor configured to convert the differential current into a second output voltage;

a first output stage configured to output the first output voltage from a first output terminal; and

a second output stage configured to output the second output voltage from a second output terminal.

2. The instrumentation amplifier according to claim 1 , wherein the first output stage includes

a first transistor of which a drain terminal is connected to the first output terminal and a first end of the second resistor and a gate terminal is connected to the first input stage, and

a first current source connected to the drain terminal of the first transistor, the first end of the second resistor, and the first output terminal, and

wherein the second output stage includes

a second transistor of which a drain terminal is connected to the second output terminal and a first end of the third resistor and a gate terminal is connected to the second input stage, and

a second current source connected to the drain terminal of the second transistor, the first end of the third resistor, and the second output terminal.

3. The instrumentation amplifier according to claim 1 , wherein the first input stage includes

a third transistor of which a gate terminal is connected to the first input terminal and a source terminal is connected to a first end of the first resistor,

a third current source connected to the source terminal of the third transistor and the first end of the first resistor,

a fourth transistor of which a drain terminal is connected to the source terminal of the third transistor, the first end of the first resistor, and a first end of the third current source,

a fourth current source connected to a source terminal of the fourth transistor and a second end of the second resistor,

a fifth current source connected to a drain terminal of the third transistor, and

a first level shift circuit of which a first end is connected to the drain terminal of the third transistor and a second end is connected to a gate terminal of the fourth transistor, and

wherein the second input stage includes

a fifth transistor of which a gate terminal is connected to the second input terminal and a source terminal is connected to a second end of the first resistor,

a sixth current source connected to the source terminal of the fifth transistor and the second end of the first resistor,

a sixth transistor of which a drain terminal is connected to the source terminal of the fifth transistor, the second end of the first resistor, and a first end of the sixth current source,

a seventh current source connected to a source terminal of the sixth transistor and a second end of the third resistor,

an eighth current source connected to a drain terminal of the fifth transistor, and

a second level shift circuit of which a first end is connected to the drain terminal of the fifth transistor and a second end is connected to a gate terminal of the sixth transistor.

Assignments (2)
CHANGE OF ADDRESS Recorded Dec 2, 2016
From: OLYMPUS CORPORATION
To: OLYMPUS CORPORATION
Reel/Frame 040818/0205 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2015
From: HARADA, YASUNARI
To: OLYMPUS CORPORATION
Reel/Frame 036197/0979 →
Priority Claims (1)
JP 2013-084166 · Apr 12, 2013 · national
Continuity (2)
Continuation PCTJP2014051936 · Jan 29, 2014
Related Publication 20150333715A1 · Nov 19, 2015