Extended utilization area for a memory device
Methods, systems and devices for configuring access to a memory device are disclosed. The configuration of the memory device may be carried out by creating a plurality of access profiles that are adapted to optimize access to the memory device in accordance with a type of access. For example, when an application with specific memory access needs is initiated, the memory access profile that is designed for that particular access need may be utilized to configure access to the memory device. The configuration may apply to a portion of the memory device, a partition of the memory device, a single access location on the memory device, or any combination thereof.
1. A memory device comprising:
two or more predefined access profiles to determine how access to the memory device is configured for at least one usage of the memory device, wherein:
at least a first predefined access profile of the two or more predefined access profiles corresponds to a random mode of access; and
at least a second predefined access profile of the two or more predefined access profiles corresponds to a sequential mode of access;
a controller configured to:
receive one or more commands to activate at least one predefined profile of the two or more predefined access profiles associated with the memory device, wherein the one or more commands comprise a metadata portion for designating the at least one predefined access profile; and
configure, based at least in part on the one or more commands, access to the memory device in accordance with the at least one predefined access profile such that at least a portion of the memory device is configured according to the at least one predefined access profile for the at least one usage.
2. The memory device of claim 1 , wherein the controller is further configured to activate, based at least in part on the one or more commands, at least two predefined access profiles of the two or more predefined access profiles in parallel.
3. The memory device of claim 1 , wherein the at least one predefined access profile comprises a default access profile.
4. The memory device of claim 1 , wherein the controller is further configured to interleave two or more simultaneous memory access operations and to assign access priority levels to resolve conflicting interleaved memory access operations.
5. The memory device of claim 1 , wherein the at least one predefined access profile comprises the first predefined access profile.
6. The memory device of claim 1 , wherein the at least one predefined access profile comprises the second predefined access profile.
7. The memory device of claim 1 , wherein the at least one predefined access profile corresponds to at least one of:
one or more write operations;
one or more read operations; or
one or more erase operations.
8. A method comprising:
receiving one or more commands to activate at least one predefined access profile of two or more predefined access profiles associated with a memory device, the two or more predefined access profiles determining how access to the memory device is configured for at least one usage of the memory device, wherein:
at least a first predefined access profile of the two or more predefined access profiles corresponds to a random mode of access; and
at least a second predefined access profile of the two or more predefined access profiles corresponds to a sequential mode of access; and
configuring, based at least in part on the one or more commands, access to the memory device in accordance with the at least one predefined access profile such that at least a portion of the memory device is configured according to the at least one predefined access profile for the at least one usage.
9. The method of claim 8 , further comprising activating, based at least in part on the one or more commands, at least two predefined access profiles of the two or more predefined access profiles in parallel.
10. The method of claim 8 , wherein the at least one predefined access profile comprises a default access profile.
11. The method of claim 8 , further comprising:
interleaving two or more simultaneous memory access operations; and
assigning access priority levels to resolve conflicting interleaved memory access operations.
12. The method of claim 8 , wherein the at least one predefined access profile comprises the first predefined access profile.
13. The method of claim 8 , wherein the at least one predefined access profile comprises the second predefined access profile.
14. The method of claim 8 , wherein the at least one predefined access profile corresponds to at least one of:
one or more write operations;
one or more read operations; or
one or more erase operations.
15. A memory device comprising:
means for receiving one or more commands to activate at least one predefined access profile of two or more predefined access profiles associated with the memory device, the two or more predefined access profiles determining how access to the memory device is configured for at least one usage of the memory device, wherein:
at least a first predefined access profile of the two or more predefined access profiles corresponds to a random mode of access; and
at least a second predefined access profile of the two or more predefined access profiles corresponds to a sequential mode of access; and
means for configuring, based at least in part on the one or more commands, access to the memory device in accordance with the at least one predefined access profile such that at least a portion of the memory device is configured according to the at least one predefined access profile for the at least one usage.
16. The memory device of claim 15 , further comprising means for activating, based at least in part on the one or more commands, at least two predefined access profiles of the two or more predefined access profiles in parallel.
17. The memory device of claim 15 , wherein the at least one predefined access profile comprises a default access profile.
18. The memory device of claim 15 , further comprising:
means for conducting two or more simultaneous memory access operations; and
means for interleaving two or more simultaneous memory access operations.
19. The memory device of claim 15 , wherein the at least one predefined access profile comprises the first predefined access profile.
20. The memory device of claim 15 , wherein the at least one predefined access profile comprises the second predefined access profile.
21. The memory device of claim 15 , wherein the at least one predefined access profile corresponds to at least one of:
one or more write operations;
one or more read operations; or
one or more erase operations.
22. A host device, comprising:
an interface to couple the host device to a memory device; and
a controller configured with logic instructions to perform acts comprising:
determining at least one mode of access from a plurality of modes of access to be performed in association with the memory device, wherein the plurality of modes of access comprises:
a random mode of access; and
a sequential mode of access; and
sending one or more commands from the host device to the memory device that is connected to the host device, the one or more commands to activate at least one predefined access profile of two or more predefined access profiles associated with the at least one determined mode of access.
23. The host device of claim 22 , wherein the one or more commands further activate at least two predefined access profiles of the two or more predefined access profiles in parallel.
24. The host device of claim 22 , wherein the at least one predefined access profile comprises a default access profile.
25. The host device of claim 22 , wherein the at least one determined mode of access comprises a default mode of access.
26. The host device of claim 22 , wherein the determined mode of access comprises the random mode of access.
27. The host device of claim 22 , wherein the determined mode of access comprises the sequential mode of access.
28. The host device of claim 22 , wherein the determined mode of access corresponds to at least one of:
one or more write operations;
one or more read operations; or
one or more erase operations.