Semiconductor devices and packages having through electrodes

1. A semiconductor package comprising:

a first semiconductor chip including:

a first substrate having a first surface and a second surface that are opposite to each other;

a plurality of first through electrodes penetrating the first substrate and being spaced apart from each other;

a plurality of first front-side bumps disposed on the first surface of the first substrate and connected to first odd-numbered through electrodes among the first through electrodes;

a plurality of first backside bumps disposed on the second surface of the first substrate and connected to first even-numbered through electrodes among the first through electrodes; and

a second semiconductor chip including:

a second substrate having a first surface and a second surface that are opposite to each other;

a plurality of second through electrodes penetrating the second substrate and being spaced apart from each other;

a plurality of second front-side bumps disposed on the first surface of the second substrate and connected to second odd-numbered through electrodes among the second through electrodes; and

a plurality of second backside bumps disposed on the second surface of the second substrate and connected to second even-numbered through electrodes among the second through electrodes,

wherein the first and second semiconductor chips are combined with each other so that the first surface of the first substrate faces the second surface of the second substrate.

2. The semiconductor package of claim 1 ,

wherein the second backside bumps are electrically connected to the second even-numbered through electrodes, and

wherein the first front-side bumps are electrically connected to the first odd-numbered through electrodes.

3. The semiconductor package of claim 1 ,

wherein each of the first front-side bumps includes a first metal layer and a first contact metal layer which are sequentially stacked on one of the first odd-numbered through electrodes, and

wherein each of the first backside bumps includes a second metal layer and a second contact metal layer which are sequentially stacked on one of the first even-numbered through electrodes.

4. The semiconductor package of claim 1 ,

wherein each of the second front-side bumps includes a third metal layer and a third contact metal layer which are sequentially stacked on one of the second odd-numbered through electrodes, and

wherein each of the second backside bumps includes a fourth metal layer and a fourth contact metal layer which are sequentially stacked on one of the second even-numbered through electrodes.

5. The semiconductor package of claim 3 , wherein the first contact metal layers of the first front-side bumps contact the second semiconductor chip.

6. The semiconductor package of claim 3 , wherein the first contact metal layers of the first front-side bumps are electrically connected to the second odd-numbered through electrodes.

7. The semiconductor package of claim 4 , wherein the fourth contact metal layers of the second backside bumps contact the first semiconductor chip.

8. The semiconductor package of claim 4 , wherein the fourth contact metal layers of the second backside bumps are electrically connected to the first even-numbered through electrodes.

9. The semiconductor package of claim 1 ,

wherein the first semiconductor chip further includes:

a first insulation layer disposed on the first surface of the first substrate; and

a plurality of conductive contact pads disposed in the first insulation layer and being in contact with the first through electrodes,

wherein the second semiconductor chip further includes:

a second insulation layer disposed on the first surface of the second substrate; and

a plurality of conductive contact pads disposed in the second insulation layer and being in contact the second through electrodes,

wherein the first surfaces of the first and second substrates are front-side surfaces of the first and second substrates adjacent to active regions defined in the first and second substrates,

wherein the second surfaces of the first and second substrates are backside surfaces of the first and second substrates,

wherein the first front-side bumps are disposed on the contact pads of the first semiconductor chip, and

wherein the second front-side bumps are disposed on the contact pads of the second semiconductor chip.

10. The semiconductor package of claim 9 ,

wherein the contact pads of the first semiconductor chip include first contact pads connected to the first odd-numbered through electrodes and second contact pads connected to the first even-numbered through electrodes, and

wherein the contact pads of the second semiconductor chip include third contact pads electrically connected to the second odd-numbered through electrodes and fourth contact pads electrically connected to the second even-numbered through electrodes.

11. The semiconductor package of claim 10 , wherein each of the first and second semiconductor chips further includes first diffusion barrier patterns that are disposed on each of the first, second, third and fourth contact pads.

12. The semiconductor package of claim 11 , wherein each of the first diffusion barrier patterns includes a nickel material.

13. The semiconductor package of claim 11 , wherein the second backside bumps contact the first diffusion barrier patterns of the first semiconductor chip.

14. The semiconductor package of claim 3 , wherein each of the first and second semiconductor chips further includes second diffusion barrier patterns that are disposed on the second surface and cover the odd-numbered through electrodes.

15. The semiconductor package of claim 14 , wherein the first contact metal layers of the first front-side bumps contact the second diffusion barrier patterns of the second semiconductor chip.

16. The semiconductor package of claim 13 , wherein each of the second diffusion barrier patterns includes a nickel material.