IP Library › Granted Patent US 9,372,528
Granted Patent B2
US 9,372,528 · App. 13/481,861 · Granted Jun 21, 2016

Universal serial bus (USB) 3.0 compatible host with lower operation power consumption and method for reducing operation power consumption of a USB 3.0 compatible host

Inventors: Chih-Hung Huang (Taipei, TW); Chien-Cheng Kuo (Taipei, TW); Shih-Min Hsu (Taipei, TW)
Assignee: eEver Technology, Inc.
G06F1/3287G06F1/3253Y02B60/1235Y02B60/1282
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Quick Facts
Patent No.
US 9,372,528
App. No.
13/481,861
Granted
Jun 21, 2016
Kind
B2
Abstract

A USB 3.0 host with low power consumption includes a super speed circuit, a non-super speed circuit, and a control module. The super speed circuit is used for transmitting data at a first transmission speed. A default state of the super speed circuit is turning-off. The non-super speed circuit is used for transmitting data at a second transmission speed, a third transmission speed, or a fourth transmission speed. The first transmission speed is faster than the second transmission speed, the third transmission speed, and the fourth transmission speed. The control module is used for detecting whether a USB peripheral device is connected to the USB 3.0 host, and controlling turning-on and turning-off of the super speed circuit.

Claims (15)

1. A Universal Serial Bus (USB) 3.0 compatible host with lower operation power consumption, the USB 3.0 compatible host comprising:

a super speed circuit for transmitting data at a first transmission speed, wherein a default state of the super speed circuit is turned off when a USB compatible peripheral device is not yet connected to the USB 3.0 compatible host;

a non-super speed circuit for transmitting data at a second transmission speed, a third transmission speed, or a fourth transmission speed, wherein the first transmission speed is faster than the second transmission speed, the third transmission speed, and the fourth transmission speed;

a control circuit turning on the super speed circuit which exits the default state when the USB compatible peripheral device being connected to the USB 3.0 compatible host and transmitting a reset signal to the USB compatible peripheral device; and

wherein the USB compatible peripheral device utilizes a non-super speed circuit included by the USB compatible peripheral device to communicate with the non-super speed circuit of the USB 3.0 compatible host according to the reset signal when the USB compatible peripheral device is the non-USB 3.0 peripheral device, and the control circuit turns off the super speed circuit of the USB 3.0 compatible host when the USB compatible peripheral device is the non-USB 3.0 peripheral device.

2. The USB 3.0 compatible host of claim 1 , wherein the USB compatible peripheral device utilizes a super speed circuit included by the USB compatible peripheral device to communicate with the super speed circuit of the USB 3.0 compatible host according to the reset signal when the USB compatible peripheral device is the USB 3.0 compatible peripheral device.

3. The USB 3.0 compatible host of claim 2 , wherein the control circuit turns off the non-super speed circuit of the USB 3.0 compatible host when the USB compatible peripheral device is the USB 3.0 compatible peripheral device.

4. A method for reducing operation power consumption of a USB 3.0 compatible host, the method comprising:

making a super speed circuit of a USB 3.0 compatible host enter a default state when a USB compatible peripheral device is not yet connected to the USB 3.0 compatible host, wherein the default state of the super speed circuit is turned off;

a control circuit turning on the super speed circuit of the USB 3.0 compatible host which exits the default state when a USB compatible peripheral device being connected to the USB 3.0 compatible host and transmitting a reset signal to the USB compatible peripheral device; and

wherein the USB compatible peripheral device utilizes a super speed circuit included by the USB compatible peripheral device to communicate with the super speed circuit of the USB 3.0 compatible host according to the reset signal when the USB compatible peripheral device is the USB 3.0 compatible peripheral device;

wherein the USB compatible peripheral device utilizes a non-super speed circuit included by the USB compatible peripheral device to communicate with a non-super speed circuit of the USB 3.0 compatible host according to the reset signal when the USB compatible peripheral device is the non-USB 3.0 peripheral device, and the control circuit turns off the non-super speed circuit of the USB 3.0 compatible host when the USB compatible peripheral device is the USB 3.0 compatible peripheral device.

5. The method of claim 4 , wherein the control circuit turns off the super speed circuit of the USB 3.0 compatible host when the USB compatible peripheral device is the non-USB 3.0 peripheral device.

6. The method of claim 4 , further comprising:

the control circuit turning off the super speed circuit of the USB 3.0 compatible host again when the USB compatible peripheral device is disconnected from the USB 3.0 compatible host.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2016
From: ETRON TECHNOLOGY, INC.
To: EEVER TECHNOLOGY, INC.
Reel/Frame 037771/0774 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2012
From: HUANG, CHIH-HUNG; KUO, CHIEN-CHENG; HSU, SHIH-MIN
To: ETRON TECHNOLOGY, INC.
Reel/Frame 028276/0486 →
Priority Claims (2)
TW 100121025 A · Jun 16, 2011 · national
TW 100126990 A · Jul 29, 2011 · national
Continuity (1)
Related Publication 20120324261A1 · Dec 20, 2012