Amplifier voltage limiting using punch-through effect
Disclosed herein are systems and method for voltage clamping in semiconductor circuits using through-silicon via (TSV) positioning. A semiconductor die is disclosed that includes a silicon substrate, a bipolar transistor having collector, emitter, base and sub-collector regions disposed on the substrate, and a through-silicon via (TSV) positioned within 35 μm of the sub-collector region in order to clamp a peak voltage of the bipolar transistor at a voltage limit level.
1. A semiconductor die comprising:
a silicon substrate;
a bipolar transistor having collector, emitter, base and sub-collector regions disposed on the substrate; and
a voltage-clamping through-silicon via (TSV) formed at a position within 20 μm of the sub-collector region and configured to clamp a peak voltage of the bipolar transistor at a predetermined voltage limit level, the position being selected to provide said clamping of the peak voltage at the predetermined voltage limit level.
2. The semiconductor die of claim 1 wherein the TSV is disposed a distance of between approximately 15-20 μm from the sub-collector region of the bipolar transistor.
3. The semiconductor die of claim 1 further comprising a backside metal layer disposed on a backside of the silicon substrate, the silicon substrate being dimensioned such that a distance between the backside metal layer and the sub-collection region is less than 20 μm.
4. The semiconductor die of claim 1 wherein the TSV is disposed a distance of between approximately 10-15 μm from the sub-collector region of the bipolar transistor.
5. The semiconductor die of claim 1 wherein the voltage limit level is between approximately 4-9 volts.
6. The semiconductor die of claim 1 wherein the bipolar transistor is a bipolar transistor having a silicon or silicon-germanium alloy base.
7. The semiconductor die of claim 1 wherein the silicon substrate includes a high-resistivity portion.
8. The semiconductor die of claim 7 wherein the bipolar transistor is disposed above the high-resistivity portion.
9. The semiconductor die of claim 7 wherein the high-resistivity portion has a resistivity value greater than 500 Ohm*cm.
10. The semiconductor die of claim 7 wherein the high-resistivity portion has a resistivity of approximately 1 kOhm*cm.
11. The semiconductor die of claim 1 wherein the bipolar transistor is a component of a power amplifier.
12. A radio-frequency (RF) module comprising:
a packaging substrate configured to receive a plurality of components;
a die mounted on the packaging substrate, the die including a power amplifier including a bipolar transistor having collector, emitter, base and sub-collector regions, the die further including a voltage-clamping through-silicon via (TSV) formed at a position within 20 μm of the sub-collector region and configured to clamp a peak voltage of the bipolar transistor at a predetermined voltage limit level, the position being selected to provide said clamping of the peak voltage at the predetermined voltage limit level; and
a plurality of connectors configured to provide electrical connections between the die and the packaging substrate.
13. The RF module of claim 12 , wherein the TSV is disposed a distance of between approximately 15-20 μm from the sub-collector region of the bipolar transistor.
14. The RF module of claim 12 , further comprising a backside metal layer disposed on a backside of the silicon substrate, the silicon substrate being dimensioned such that a distance between the backside metal layer and the sub-collection region is less than 20 μm.
15. The RF module of claim 12 , wherein the TSV is disposed a distance of between approximately 10-15 μm from the sub-collector region of the bipolar transistor.