Adaptively limiting a maximum operating frequency in a multicore processor

1. A processor comprising:

a plurality of cores each to independently execute instructions; and

a power control unit (PCU) coupled to the plurality of cores to control power consumption of the processor, the PCU including a control logic to limit a turbo mode frequency of at least one of the plurality of cores to be below a configured maximum turbo mode frequency based at least in part on a number of performance state transitions occurring to the at least one core due to low power state exits of others of the plurality of cores.

2. The processor of claim 1 , wherein the control logic is to update the number of performance state transitions when the PCU causes the at least one core to incur a performance state transition when a second core exits a low power state.

3. The processor of claim 2 , wherein the control logic is to limit the turbo mode frequency when the number of performance state transitions exceeds a first threshold, responsive to the second core low power state exit.

4. The processor of claim 1 , further comprising a first storage of the processor to store the configured maximum turbo mode frequency.

5. The processor of claim 4 , further comprising a second storage of the processor to store a table including a plurality of entries each associating a number of active cores with a maximum turbo mode frequency.

6. The processor of claim 5 , wherein the control logic is to limit the turbo mode frequency to further be below a maximum turbo mode frequency obtained from one of the plurality of entries of the table.

7. The processor of claim 5 , further comprising a third storage to store a maximum ceiling frequency corresponding to the turbo mode frequency limit.

8. A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

determining whether a performance state transition occurs for a first core of a multicore processor when another core of the multicore processor exits a low power state;

responsive to the performance state transition, updating a forced transition count;

determining whether the forced transition count exceeds a first threshold; and

if so, reducing a maximum ceiling frequency value corresponding to a maximum turbo mode frequency at which the first core is to operate.

9. The non-transitory machine-readable medium of claim 8 , wherein the method further comprises determining whether the performance state transition occurs responsive to the another core exiting the low power state.

10. The non-transitory machine-readable medium of claim 8 , wherein the method further comprises reducing the maximum ceiling frequency value to be less than a configured maximum turbo mode frequency value and a maximum turbo mode frequency obtained from one of a plurality of entries of a table.

11. The non-transitory machine-readable medium of claim 8 , wherein the method further comprises: determining if the forced transition count exceeds a second threshold; and if so, reducing the maximum ceiling frequency value.

12. The non-transitory machine-readable medium of claim 11 , wherein the second threshold is less than the first threshold.

13. The non-transitory machine-readable medium of claim 11 , wherein the method further comprises increasing the maximum ceiling frequency value if the forced transition count is less than the second threshold.

14. The non-transitory machine-readable medium of claim 13 , wherein the method further comprises increasing the maximum ceiling frequency value further when a duration since a prior maximum ceiling frequency value reduction exceeds a third threshold.

15. A system comprising:

a multicore processor comprising:

a plurality of cores each to independently execute instructions; and

a power control unit (PCU) coupled to the plurality of cores to control power consumption of the multicore processor, the PCU including a control logic to reduce a maximum operating frequency of the multicore processor if a first number of forced performance state transitions occurs in a first time period or a second number of forced performance state transitions occurs in a second time period;

a power supply unit coupled to the multicore processor to provide a regulated voltage to the multicore processor; and

a dynamic random access memory (DRAM) coupled to the multicore processor.

16. The system of claim 15 , wherein the control logic is to compare the first number of forced performance state transitions to a first threshold and to reduce the maximum operating frequency based on the comparison, responsive to a low power state exit of a first core of the plurality of cores.

17. The system of claim 16 , wherein the control logic is to compare the second number of forced performance state transitions to a second threshold and to reduce the maximum operating frequency based on the comparison, responsive to expiration of a time duration, and wherein the second threshold is less than the first threshold.

18. The system of claim 17 , wherein the control logic is to increase the maximum operating frequency if the second number of forced performance state transitions is less than the second threshold and a duration since a prior maximum operating frequency reduction exceeds a third threshold.

19. The system of claim 15 , wherein the control logic is to reduce the maximum operating frequency below a configured maximum operating frequency and below a permissible maximum operating frequency based on a number of active cores of the multicore processor.

20. The system of claim 19 , further comprising a first storage to store the configured maximum operating frequency, a second storage to store a table including a plurality of entries each associating a number of active cores with the permissible maximum operating frequency, and a third storage to store the reduced maximum operating frequency.