IP Library Granted Patent US 9,378,104
Granted Patent B2
US 9,378,104 · App. 14/556,735 · Granted Jun 28, 2016

Mirroring in three-dimensional stacked memory

Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary (Bangalore, IN); Saravanan Sethuraman (Bangalore, IN); Kenneth L. Wright (Austin, TX)
Assignee: International Business Machines Corporation
G06F11/2058G06F11/2069G11C29/50004G11C29/783G11C29/83G11C2029/5004
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Quick Facts
Patent No.
US 9,378,104
App. No.
14/556,735
Granted
Jun 28, 2016
Kind
B2
Abstract

A method for mirroring in three-dimensional-stacked memory includes receiving a plurality of thermal profiles from a plurality of memory chips. The method also includes ranking the plurality of memory chips in a first ranked list of memory chips as a function of the plurality of thermal profiles and forming a first group of memory chips from the plurality of memory chips based on the first ranked list of memory chips. The method also includes forming a second group of memory chips from the plurality of memory chips distinct from the first group of memory chips based on the first ranked list of memory chips. The method also includes pairing a first memory chip from the first group of memory chips and a second memory chip from the second group of memory chips, and mirroring the pairing of memory chips.

Claims (27)

1. A method comprising:

receiving a plurality of thermal profiles from a plurality of three-dimensional (3D)-stacked memory chips;

ranking the plurality of memory chips in a first ranked list of memory chips as a function of the plurality of thermal profiles;

forming a first group of memory chips from the plurality of memory chips based on the first ranked list of memory chips;

forming a second group of memory chips from the plurality of memory chips distinct from the first group of memory chips based on the first ranked list of memory chips;

pairing a first memory chip from the first group of memory chips and a second memory chip from the second group of memory chips; and

mirroring the pairing of memory chips.

2. The method of claim 1 , further comprising:

creating a first thermal look-up table based on the received plurality of thermal profiles; and

storing the plurality of thermal profiles for the plurality of memory chips in the first thermal look-up table.

3. The method of claim 2 , wherein storing the plurality of thermal profiles includes associating a rank from the first ranked list with a thermal profile.

4. The method of claim 2 , wherein the first thermal look-up table contains vital product data (“VPD”) of a memory chip from the plurality of memory chips.

5. The method of claim 2 , wherein the first ranked list of memory chips has a first half and a second half both defined by the first ranked list.

6. The method of claim 5 , wherein the memory chips of the first group of memory chips stored in the first thermal look-up table correspond to the first half of the first ranked list.

7. The method of claim 5 , wherein the first half of the first ranked list is colder than the second half.

8. The method of claim 5 , wherein the memory chips of the second group of memory chips stored in the first thermal look-up table correspond to the second half of the first ranked list.

9. The method of claim 5 , further comprising:

measuring the plurality of thermal profiles in the first ranked list of memory chips; and

ranking the plurality of memory chips in a second ranked list as a function of the plurality of thermal profiles.

10. The method of claim 5 , wherein pairing a first memory chip from the first group of memory chips and a second memory chip from the second group of memory chips includes the first memory chip is the coldest memory chip from the first half, and the second memory chip is the coldest memory chip from the second half.

11. The method of claim 1 , wherein mirroring the pairing of memory chips includes:

writing to a memory chip from the pairing of memory chips, and

writing to and reading from a second memory chip from the pairing of memory chips.

12. The method of claim 1 , wherein ranking the plurality of memory chips includes:

ranking a plurality of N memory chips with corresponding thermal profiles, from 1to N, with 1 corresponding to the coldest memory chip and N corresponding to the hottest memory chip;

assigning the memory chip from the first group of memory chips as the median ranked (N/2)+1 memory chip of the N memory chips; and

assigning the memory chip from the second group of memory chips as the first memory chip of the N memory chips.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 1, 2014
From: CHINNAKKONDA VIDYAPOORNACHARY, DIYANESH B.; SETHURAMAN, SARAVANAN; WRIGHT, KENNETH L.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 034289/0666 →
Continuity (2)
Continuation 14538966 · Nov 12, 2014
Related Publication 20160132408A1 · May 12, 2016