IP Library Granted Patent US 9,378,697
Granted Patent B2
US 9,378,697 · App. 14/375,837 · Granted Jun 28, 2016

Drive device and display device

Inventors: Akizumi Fujioka (Osaka, JP); Toshihiro Yanagi (Osaka, JP); Satoshi Ihida (Osaka, JP); Kazuki Takahashi (Osaka, JP); Taketoshi Nakano (Osaka, JP)
Assignee: Sharp Kabushiki Kaisha
G09G3/3674G09G3/3648G09G2310/067G09G2320/043G09G2330/021G09G2340/0435
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Quick Facts
Patent No.
US 9,378,697
App. No.
14/375,837
Granted
Jun 28, 2016
Kind
B2
Abstract

Included are: refresh a rate changing section ( 15 ) for changing a refresh rate of a display panel ( 2 ) by configuring settings for scan periods during each of which a plurality of gate signal lines (G) of the display panel ( 2 ) are sequentially scanned and for pause periods during each of which sequential scanning of the plurality of gate signal lines (G) is suspended; and a drive amount control section ( 20 ) for controlling, in accordance with a ratio of the scan periods to the pause periods, drive time during which each of the gate signal lines is driven in each of the scan periods.

Claims (11)

1. A drive device for driving a display panel having a plurality of pixels, comprising:

a timing controller that:

changes a refresh rate of the display panel by configuring settings for scan periods during each of which a plurality of gate signal lines of the display panel are sequentially scanned and for pause periods during each of which sequential scanning of the plurality of gate signal lines is suspended; and

controls, in accordance with a ratio of the scan periods to the pause periods, drive time during which each of the gate signal lines is driven in each of the scan periods such that a ratio of the drive time of each of the gate signal lines to non-drive time other than the drive time of the respective gate signal line is kept constant both prior to and subsequent to a change of the refresh rate.

2. The drive device as set forth in claim 1 , wherein for each of the plurality of gate signal lines, the timing controller controls a pulse width of a drive pulse on the gate signal line and thereby controls drive time of the gate signal line.

3. The drive device as set forth in claim 1 , wherein for each of the plurality of gate signal lines, the timing controller controls a pulse number of drive pulses on the gate signal line and thereby controls drive time of the gate signal line.

4. A display device comprising:

a display panel having a plurality of pixels; and

a drive device as set forth in claim 1 .

5. The display device as set forth in claim 4 , wherein each of the plurality of pixels has a switching element whose semiconductor layer is made of an oxide semiconductor.

6. The display device as set forth in claim 5 , wherein the oxide semiconductor is an oxide composed of indium (In), gallium (Ga), and zinc (Zn).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2014
From: FUJIOKA, AKIZUMI; YANAGI, TOSHIHIRO; IHIDA, SATOSHI; TAKAHASHI, KAZUKI; NAKANO, TAKETOSHI
To: SHARP KABUSHIKI KAISHA
Reel/Frame 033434/0045 →
Priority Claims (1)
JP 2012-034516 · Feb 20, 2012 · national
Continuity (1)
Related Publication 20140368492A1 · Dec 18, 2014