IP Library › Granted Patent US 9,378,976
Granted Patent B2
US 9,378,976 · App. 14/677,673 · Granted Jun 28, 2016

Method for forming interconnects

Inventor: Roey Shaviv (Palo Alto, CA)
Assignee: APPLIED Materials, Inc.
H01L21/31144H01L21/31111H01L21/3212H01L21/7684H01L21/7685H01L21/76802H01L21/76822H01L21/76843H01L21/76871H01L21/76877H01L21/76882H01L23/5329H01L23/53295H01L23/5226H01L23/53223H01L23/53238H01L23/53252H01L23/53266
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Quick Facts
Patent No.
US 9,378,976
App. No.
14/677,673
Granted
Jun 28, 2016
Kind
B2
Abstract

A conductive interconnect including trenches ( 110 ) and ( 186 ) and vias ( 202 ) are formed in a workpiece ( 100 ) by applying a dielectric film stack ( 120 ) over the workpiece, and thereafter applying photoresist ( 140 ) over the film stack. Trenches ( 142 ) are patterned in the photoresist, wherein the trenches are in segments disposed end-to-end to each other. The segments are longitudinally spaced apart from each other at locations where the vias ( 202 ) are to be located. The trenches are etched into the dielectric film stack, and then filled with conductive material to form metal line segments ( 186 ). Vias ( 192 ) are patterned in the gaps separating the adjacent ends of the longitudinally-related lines ( 186 ). The patterned vias are etched and then filled with a conductive material, with the ends of the adjacent line segments ( 186 ) serving to accurately locate the vias, in a direction along the lengths of the trenches.

Claims (44)

1. A method of forming an interconnect including trenches and vias in a workpiece, the method comprising:

applying a dielectric film stack on the workpiece;

applying a hard mask over the dielectric film stack;

applying a photoresist over the hard mask;

patterning trenches in the photoresist, the trenches being patterned in longitudinal segments disposed end-to-end to each other, the segments longitudinally spaced apart from each other at locations where vias are to be located;

etching trenches into the dielectric film stack;

filling the trenches with a conductive material;

patterning vias in the gaps separating the ends of longitudinally related filled trenches;

etching the patterned vias in the workpiece; and

filling the etched vias with the conductive material.

2. A method of forming an interconnect including trenches and vias in a workpiece, the method comprising:

applying a dielectric film stack on the workpiece;

applying a hard mask over the dielectric film stack;

applying a photoresist over the hard mask;

patterning vias in the photoresist defining gaps separating vias;

etching the patterned vias in the workpiece;

filling the etched vias with a conductive material;

patterning trenches in the photoresist, the trenches being patterned in longitudinal segments disposed end-to-end to each other in the gaps separating the vias, the segments longitudinally spaced apart from each other at the locations of the vias;

etching trenches into the dielectric film stack; and

filling the trenches with the conductive material.

3. A semiconductor workpiece comprising trenches and vias produced by:

applying a dielectric composition on the workpiece;

applying a hard mask over the dielectric composition;

applying a photoresist over the hard mask;

patterning trenches in the photoresist, the trenches being patterned in longitudinally arranged segments disposed end-to-end to each other, the longitudinal segments spaced apart from each other at locations where vias are to be located;

etching trenches into the dielectric composition;

filling the trenches with a conductive material;

patterning vias in the gaps separating the ends of longitudinally related trenches;

etching the patterned vias in the dielectric composition; and

filling the etched vias with the conductive material.

4. The workpiece of claim 3 , wherein, after formation of the trenches, the photoresist is applied over the trenches, and the vias are patterned on such photoresist.

5. The workpiece of claim 3 , wherein, after the etching of the vias, a barrier layer is deposited over the via sidewall surface.

6. The workpiece of claim 3 , wherein a metal overburden of the via fill material is applied to the workpiece.

7. The workpiece of claim 3 , further comprising removing the overburden to reduce the height of the workpiece to expose the conductive material filled trenches and aligned vias.

8. A semiconductor workpiece comprising trenches and vias produced by:

applying a dielectric film stack on the workpiece;

applying a hard mask over the dielectric film stack;

applying a photoresist over the hard mask;

patterning vias in the photoresist defining gaps separating the vias;

etching the patterned vias in the workpiece;

filling the etched vias with a conductive material;

patterning trenches in the photoresist, the trenches being patterned in longitudinal segments disposed end-to-end to each other in the gaps separating the vias, the segments longitudinally spaced apart from each other at the locations of the vias;

etching trenches into the dielectric film stack; and

filling the trenches with the conductive material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2015
From: SHAVIV, ROEY
To: APPLIED MATERIALS, INC.
Reel/Frame 035846/0803 →
Continuity (2)
Provisional Application 61974332 · Apr 2, 2014
Related Publication 20150287675A1 · Oct 8, 2015