Fin field effect transistor
A method of fabricating a fin field effect transistor (FinFET) including forming a first insulation region and a second insulation region and fin there between. The method further includes forming a gate stack over a portion of the fin and over a portion of the first and second insulation regions. The method further includes tapering the top surfaces of the first and second insulation regions not covered by the gate stack.
1. A method of fabricating a fin field effect transistor (FinFET), the method comprising:
forming a first insulation region and a second insulation region having respective top surfaces;
forming a fin between the first and second insulation regions, wherein the top surfaces of the first and second insulation regions are below a top surface of the fin;
forming a gate stack over a portion of the fin and over a portion of the first and second insulation regions; and
tapering the top surfaces of the first and second insulation regions not covered by the gate stack.
2. The method of claim 1 , wherein forming the gate stack comprises:
forming a gate electrode layer; and
forming a pair of spacers, wherein a first spacer of the pair of spacers is on a first side of the gate electrode layer, and a second spacer of the pair of spacers is on a second side of the gate electrode layer, the second side being opposite the first side.
3. The method of claim 1 , further comprising etching a portion of the fin exposed by the gate stack using the gate stack as a mask.
4. The method of claim 1 , wherein etching the portion of the fin comprises etching the portion of the fin using at least one of HBr or Cl 2 gas.
5. The method of claim 1 , wherein tapering the top surfaces of the first and second insulation regions comprises:
forming a first surface substantially parallel to a top surface of the fin; and
forming a second surface at an angle to the first surface.
6. The method of claim 1 , wherein tapering the top surfaces of the first and second insulation region comprises forming a continuously curved surface.
7. The method of claim 1 , further comprising growing a strained material over the tapered top surfaces of the first and second insulation regions at a temperature ranging from about 400° C. to about 800° C.
8. The method of claim 7 , wherein growing the strained layer comprises growing the strained layer including at least one of silicon carbon or silicon germanium.
9. The method of claim 7 , wherein growing the strained material comprises growing the strained material over the tapered top surfaces in a direction substantially parallel to a top surface of the fin.
10. The method of claim 7 , wherein the growing the strained material including forming an interface between the strained material and tapered top surfaces of the first and second insulating regions.
11. A method of fabricating a fin field effect transistor (FinFET), the method comprising:
providing a substrate having an insulation region and a fin abutting the insulation region;
recessing a portion of the fin to form a recessed portion of the fin below a top surface of the insulation region;
etching at least a portion of the top surface of insulation region adjacent the recessed portion of the fin; and
forming a semiconductor material over the recessed portion of the fin and the etched top surfaces of the insulation region.
12. The method of claim 11 , wherein the etching is a wet etching process.
13. The method of claim 11 , wherein the forming the semiconductor material includes an epitaxial growth process including the semiconductor material formed on the recessed portion of the fin merging with another semiconductor material grown on an adjacent fin.
14. The method of claim 11 , wherein the forming the semiconductor material includes a chemical vapor deposition (CVD) process.
15. The method of claim 11 , wherein the etching is a dry etching process.
16. The method of claim 11 , wherein the recessing the portion of the fin includes using spacer elements of a gate stack as a masking element during the recessing.
17. A method of fabricating a semiconductor device, the method comprising:
providing a substrate having a first insulation region and a second insulation region having respective top surfaces, and a fin between the first and second insulation regions;
forming a gate stack over a first portion of the fin and extending over a first region of the first and second insulating regions, wherein the first region of the first and second insulating regions have top surfaces having a first height;
recessing a second portion of the fin adjacent the first portion of fin, wherein the recessing exposes sidewalls of a second region of each of the first and second insulation regions;
etching the second region of the first and second insulation regions to form top surfaces having a second height, wherein the second height is less than the first height; and
growing a semiconductor material over the recessed second portion of the fin and etched second region of the first and second insulation regions.
18. The method of claim 17 , wherein the etching the second region of the first and second insulating regions forms tapered top surfaces of the first and second insulation regions.
19. The method of claim 18 , wherein the etching the second region of the first and second insulating regions forms tapered top surfaces of the first and second insulation regions and wherein the tapered top surfaces are curved surfaces.
20. The method of claim 18 , wherein the tapered top surfaces include an upper surface and two oblique surfaces.