Semiconductor integrated circuit, current control method, ad converter, solid-state imaging device, and electronic system
A semiconductor integrated circuit includes: a plurality of current sources including a first transistor individually connected to a power source line and a bias line; and a plurality of bias blocks including a second transistor configured to constitute a current mirror circuit together with the first transistor, and to divide a reference current to be a reference of the current sources so that the reference current flows through the bias line.
1. A solid-state imaging device including a semiconductor integrated circuit comprising:
the semiconductor integrated circuit comprising:
a first current source transistor between a first bias block transistor and a second bias block transistor, a gate terminal of the first bias block transistor being electrically connected to a gate terminal of the first current source transistor; and
a bias line electrically connected to a drain terminal of the first bias block transistor and to the gate terminal of the first bias block transistor, a gate terminal of the second bias block transistor being electrically connected to a drain terminal of the second bias block transistor and to the bias line;
an analog-to-digital conversion section configured to convert an analog signal to a digital signal on the basis of a reference signal generated by the semiconductor integrated circuit; and
a pixel array section that converts incident light into the analog signal,
wherein the first bias block transistor and the second bias block transistor are disposed in a manner that a reference current to be a reference of the first current source transistor is divided into two sub reference currents and one of the two sub reference currents flows through the bias line.
2. The solid-state imaging device according to claim 1 , wherein the first current source transistor, the first bias block transistor, and the second bias block transistor are PMOS transistors.
3. The solid-state imaging device according to claim 1 , wherein the first current source transistor, the first bias block transistor, and the second bias block transistor are NMOS transistors.
4. The solid-state imaging device according to claim 1 , further comprising:
a voltage line electrically connected to a source terminal of the first current source transistor, to a source terminal of the first bias block transistor and to a source terminal of the second bias block transistor.
5. The solid-state imaging device according to claim 4 , wherein the voltage line is a power source line.
6. The solid-state imaging device according to claim 4 , wherein the voltage line is a ground line.
7. The solid-state imaging device according to claim 1 , further comprising:
a third bias block transistor between the first bias block transistor and the second bias block transistor.
8. The solid-state imaging device according to claim 7 , wherein the bias line is electrically connected to a gate terminal of the third bias block transistor and to a drain terminal of the third bias block transistor.
9. The solid-state imaging device according to claim 1 , further comprising:
a second current source transistor between the first current source transistor and the second bias block transistor.
10. The solid-state imaging device according to claim 9 , wherein a gate terminal of the first current source transistor is electrically connected to a gate terminal of the second current source transistor.
11. The solid-state imaging device according to claim 1 , wherein a drain terminal of the first current source transistor is electrically connected to a source terminal of a first switching element.
12. The solid-state imaging device according to claim 11 , wherein a drain terminal of the first switching element is electrically connected to a drain terminal of a second switching element.
13. The solid-state imaging device according to claim 12 , wherein a source terminal of the second switching element is electrically connected to a drain terminal of a second current source transistor.
14. The solid-state imaging device according to claim 11 , wherein an input terminal of an inverter is electrically connected to a gate terminal of a complementary switching element.
15. The solid-state imaging device according to claim 14 , wherein a source terminal of the complementary switching element is electrically connected to the source terminal of the first switching element.
16. The solid-state imaging device according to claim 1 further comprising:
an optical section that captures the incident light and forms an image on an imaging surface of the solid-state imaging device.