IP Library Granted Patent US 9,383,813
Granted Patent B2
US 9,383,813 · App. 14/937,296 · Granted Jul 5, 2016

Dynamic control of reduced voltage state of graphics controller component of memory controller

Inventors: Eric C. Samson (Folsom, CA); Aditya Navale (El Dorado Hills, CA)
Assignee: INTEL CORPORATION
G06F1/3296G06F1/324G06F1/3218G06F1/3237Y02B60/1217Y02B60/1221Y02B60/1285Y02B60/32
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Quick Facts
Patent No.
US 9,383,813
App. No.
14/937,296
Granted
Jul 5, 2016
Kind
B2
Abstract

A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller. The reduction in voltage may cause the voltage to be reduced below a voltage level required to maintain context information in the graphics controller component.

Claims (36)

1. A method comprising:

receiving a first command indicating that a processor has entered a process associated with reduced graphics processing;

in response to the received first command, storing context information in an external memory;

after said storing, disabling clock signals for a graphics controller component;

after said storing, reducing a voltage applied to the graphics controller component, said reducing causing the voltage to be reduced below a voltage level required to maintain said context information in the graphics controller component;

after said reducing, detecting issuance of a second command for the graphics controller component; and

in response to detecting issuance of the second command, increasing the voltage applied to the graphics controller component, said increasing causing the voltage to be increased to a voltage level required to support full operation of the graphics controller component.

2. The method of claim 1 , further comprising:

after said increasing, enabling the clock signals for said graphics controller component.

3. The method of claim 2 , further comprising:

after said enabling, transferring said context information from said external memory to said graphics controller component.

4. The method of claim 1 , further comprising:

enabling the clock signals for said graphics controller component after detecting issuance of the second command and prior to said increasing.

5. An apparatus comprising a memory controller, the memory controller including a graphics controller component, and the memory controller also including a power management controller for controlling a supply of power for at least a portion of the memory controller, the power management controller operative to:

receive a first command indicating that a processor has entered a process associated with reduced graphics processing;

in response to receiving the first command, store context information in an external memory;

after said storing, disable clock signals for the graphics controller component;

after said storing, reduce a voltage applied to a graphics controller component of the memory controller, said reducing causing the voltage to be reduced below a voltage level required to maintain the context information in the graphics controller component;

after said reducing, detect issuance of a second command for said graphics controller component; and

in response to detecting issuance of the second command, increase the voltage applied to the graphics controller component, the increase causing the voltage to be increased to a voltage level required to support full operation of the graphics controller component.

6. The apparatus of claim 5 , wherein said power management controller is further operative to:

after the increase, enable the clock signals for said graphics controller component.

7. The apparatus of claim 6 , wherein said power management controller is further operative to:

after said enabling, transfer said context information from said external memory to said graphics controller component.

8. The apparatus of claim 5 , wherein said power management controller is further operative to:

enable the clock signals for said graphics controller component after detecting issuance of the second command and prior to said increasing.

9. A system comprising:

a memory controller; and

a graphics memory unit in communication with the memory controller;

wherein the memory controller includes a graphics controller component, and the memory controller also includes a power management controller for controlling a supply of power for at least a portion of the memory controller, the power management controller operative to:

receive a first command indicating that a processor has entered a process associated with reduced graphics processing;

in response to receiving the first command, store in an external memory context information;

after said storing, disable clock signals for said graphics controller component;

after said storing, reduce a voltage applied to the graphics controller component of the memory controller, said reducing causing the voltage to be reduced below a voltage level required to maintain the context information in the graphics controller component;

after said reducing, detect issuance of a second command for said graphics controller component; and

in response to detecting issuance of the second command, increase the voltage applied to the graphics controller component, said increasing causing the voltage to be increased to a voltage level required to support full operation of the graphics controller component.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →
Continuity (8)
Continuation 14497736 · Sep 26, 2014
Continuation 13939707 · Jul 11, 2013
Continuation 13629046 · Sep 27, 2012
Continuation 13230101 · Sep 12, 2011
Continuation 12537523 · Aug 7, 2009
Continuation 11747392 · May 11, 2007
Continuation 11024065 · Dec 28, 2004
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