Semiconductor device applicable to a multi-context programmable logic device
View Patent ↗A low-power semiconductor device is provided. A memory device applicable to a multi-context programmable logic device (PLD) includes at least memory cells the number of which is the same as the number of contexts. Output nodes of the memory cells are electrically connected to an output node of a configuration memory through different path transistors. A circuit including a transistor and a capacitor makes a gate potential of the path transistor higher than a high-level potential. This prevents a decrease in the potential of the output node of the configuration memory due to the threshold voltage of the path transistor without an increase in power consumption.
1. A semiconductor device comprising:
a first output node, and
k first circuits, where k is an integer of two or more,
wherein each of the k first circuits includes a first transistor, a second transistor, a capacitor, and a first memory circuit including a second output node,
wherein k first signals are configured to be input to the different k first circuits, respectively,
wherein, in each of the k first circuits:
one of terminals of the capacitor is electrically connected to the first output node,
the other of the terminals of the capacitor is electrically connected to a third output node,
the first transistor is configured to control conduction between the first output node and the second output node, and
the second transistor is configured to control supply of one of the k first signals to a gate of the first transistor.
2. The semiconductor device according to claim 1 , wherein in the k first circuits, an on or off state of the second transistor is controlled by a common second signal.
3. The semiconductor device according to claim 1 , further comprising a third circuit, wherein the third circuit is configured to apply a first potential to the first output node.
4. The semiconductor device according to claim 2 , further comprising a third transistor and a fourth circuit,
wherein a third signal is configured to control an on or off state of the third transistor,
wherein the third transistor is configured to control conduction between the first output node and a wiring,
wherein a first potential is supplied to the wiring,
wherein the fourth circuit is configured to generate the second signal and the k first signals.
5. The semiconductor device according to claim 1 , wherein the second transistor includes an oxide semiconductor layer where a channel is formed.
6. An electronic component comprising the semiconductor device according to claim 1 .
7. An electronic device comprising:
the semiconductor device according to claim 1 ; and
a display device.
8. An electronic device comprising:
the electronic component according to claim 6 ; and
a display device.
9. A semiconductor device comprising:
a first output node, and
a first circuit,
wherein the first circuit includes a first transistor, a second transistor, a capacitor, and a first memory circuit including a second output node,
wherein a first signal is configured to be input to the first circuit,
wherein, in the first circuit:
one of terminals of the capacitor is electrically connected to the first output node,
the other of the terminals of the capacitor is electrically connected to a third output node,
the first transistor is configured to control conduction between the first output node and the second output node, and
the second transistor is configured to control supply of the first signal to a gate of the first transistor.
10. The semiconductor device according to claim 9 , wherein in the first circuit, an on or off state of the second transistor is controlled by a common second signal.
11. The semiconductor device according to claim 9 , further comprising a third circuit, wherein the third circuit is configured to apply a first potential to the first output node.
12. The semiconductor device according to claim 10 , further comprising a third transistor and a fourth circuit,
wherein a third signal is configured to control an on or off state of the third transistor,
wherein the third transistor is configured to control conduction between the first output node and a wiring,
wherein a first potential is supplied to the wiring,
wherein the fourth circuit is configured to generate the second signal and the first signal.
13. The semiconductor device according to claim 9 , wherein the second transistor includes an oxide semiconductor layer where a channel is formed.
14. A semiconductor device comprising:
a first output node, and
k first circuits, where k is an integer of two or more,
wherein each of the k first circuits includes a first transistor, a second transistor, a capacitor, and a first memory circuit including a second output node,
wherein k first signals are configured to be input to the different k first circuits, respectively,
wherein, in each of the k first circuits:
one of terminals of the capacitor is electrically connected to the first output node,
the other of the terminals of the capacitor is electrically connected to a third output node,
the first transistor is configured to control conduction between the first output node and the second output node,
the second transistor is configured to control supply of one of the k first signals to a gate of the first transistor, and
the other of terminals of the capacitor is electrically connected to the gate of the first transistor.
15. The semiconductor device according to claim 14 , wherein in the k first circuits, an on or off state of the second transistor is controlled by a common second signal.
16. The semiconductor device according to claim 14 , further comprising a third circuit, wherein the third circuit is configured to apply a first potential to the first output node.
17. The semiconductor device according to claim 15 , further comprising a third transistor and a fourth circuit,
wherein a third signal is configured to control an on or off state of the third transistor,
wherein the third transistor is configured to control conduction between the first output node and a wiring,
wherein a first potential is supplied to the wiring,
wherein the fourth circuit is configured to generate the second signal and the k first signals.
18. The semiconductor device according to claim 14 , wherein the second transistor includes an oxide semiconductor layer where a channel is formed.