Replacement gate process
An integrated circuit containing metal replacement gates may be formed by forming a CMP stop layer over sacrificial gates, and forming a dielectric fill layer over the CMP stop layer. Dielectric material from the dielectric fill layer is removed from over the sacrificial gates using a CMP process which exposes the CMP stop layer over the sacrificial gates but does not expose the sacrificial gates. The CMP stop layer is removed from over the sacrificial gates using a plasma etch process. In one version, the plasma etch process may be selective to the CMP stop layer. In another version, the plasma etch process may be a non-selective etch process. After the sacrificial gates are exposed by the plasma etch process, the sacrificial gates are removed and the metal replacement gates are formed.
1. A method of forming an integrated circuit, comprising the steps:
providing a substrate comprising semiconductor material;
forming a gate dielectric layer over said substrate;
forming sacrificial gates over said gate dielectric layer;
forming a chemical mechanical polish (CMP) stop layer over said sacrificial gates;
forming a dielectric fill layer over said CMP stop layer, said dielectric fill layer filling spaces between said sacrificial gates;
performing a first oxide CMP process which removes dielectric material from said dielectric fill layer, planarizes a top surface of said dielectric fill layer and exposes said CMP stop layer over said sacrificial gates without removing material from said sacrificial gates;
performing a selective plasma etch process which removes said CMP stop layer and so as to expose said sacrificial gates, wherein said selective plasma etch process removes material from said CMP stop layer at least twice as quickly as material from said dielectric fill layer;
removing said sacrificial gates to form gate cavities;
performing a second oxide CMP process which lowers a top surface of said dielectric fill layer without removing material from said sacrificial gates, after said step of performing said selective plasma etch process which removes said CMP stop layer and prior to said step of removing said sacrificial gates; and
forming replacement metal gates in said gate cavities.
2. The method of claim 1 , further comprising the steps:
forming offset spacers of dielectric on lateral surfaces of said sacrificial gates; and
forming sidewall spacers on said offset spacers, prior to said step of forming said CMP stop layer.
3. The method of claim 1 , wherein said CMP stop layer includes silicon nitride.
4. The method of claim 1 , further comprising the steps:
forming gate caps of dielectric material over said sacrificial gates prior to said step of forming said CMP stop layer;
forming a layer of metal silicide at a top surface of said substrate, wherein said gate caps block formation of said metal silicide on said sacrificial gates; and
removing said gate caps after said step of performing said selective plasma etch process which removes said CMP stop layer and prior to said step of removing said sacrificial gates.
5. The method of claim 4 , wherein said gate caps include silicon nitride.
6. The method of claim 4 , wherein said gate caps include silicon oxynitride.
7. The method of claim 1 , wherein said step of forming said replacement metal gates comprises the steps:
forming a layer of work function metal over said dielectric fill layer, extending into said gate cavities;
forming a layer of gate fill metal over said layer of work function metal, extending into said gate cavities; and
removing said layer of gate fill metal and said layer of work function metal from over a top surface of said dielectric fill layer using a metal CMP process.
8. The method of claim 7 , wherein said step of removing said layer of gate fill metal and said layer of work function metal is ceased so as to form a wide top section of said replacement metal gates.
9. The method of claim 1 , further comprising the steps:
removing said gate dielectric layer after said step of removing said sacrificial gates; and
forming a high-k gate dielectric layer over said substrate in said gate cavities prior to said step of forming said replacement metal gates.
10. A method of forming an integrated circuit, comprising the steps:
providing a substrate comprising semiconductor material;
forming a gate dielectric layer over said substrate;
forming sacrificial gates having gate caps over said gate dielectric layer, said gate caps being disposed over said sacrificial gates;
forming offset spacers of dielectric on lateral surfaces of said sacrificial gates;
forming sidewall spacers on said offset spacers;
forming a layer of metal silicide at a top surface of said substrate, wherein said gate caps block formation of said metal silicide on said sacrificial gates;
forming a CMP stop layer over said sacrificial gates, said gate caps and said sidewall spacers;
forming a dielectric fill layer over said CMP stop layer, said dielectric fill layer filling spaces between said sidewall spacers;
performing a first oxide CMP process which removes dielectric material from said dielectric fill layer, planarizes a top surface of said dielectric fill layer and exposes said CMP stop layer over said sacrificial gates without removing material from said sacrificial gates;
performing a selective plasma etch process which removes said CMP stop layer and so as to expose said sacrificial gates, wherein said selective plasma etch process removes material from said CMP stop layer at least twice as quickly as material from said dielectric fill layer;
performing a second oxide CMP process which lowers a top surface of said dielectric fill layer without removing material from said sacrificial gates;
removing said sacrificial gates to form gate cavities;
removing said gate dielectric layer;
forming a high-k gate dielectric layer over said substrate in said gate cavities; and
forming replacement metal gates over said high-k gate dielectric layer in said gate cavities.
11. The method of claim 10 , wherein said CMP stop layer includes silicon nitride.