Semiconductor device
The termination region includes a ring region (LNFLR). A plurality of ring-shaped P-type ring layers are regularly arranged in the ring region (LNFLR). The ring region (LNFLR) is divided into a plurality of units which include the plurality of P-type ring layers respectively. A width of each unit is constant. A total number of P-type impurities in the ring region (LNFLR) is N, the target withstand voltage is BV [V], a width of each unit is SandL [μm], and the number of the plurality of units is num, following relationships are satisfied. N≧(M×BV) γ , M=10 4 to 10 5 , γ=0.55 to 1.95, SandL×num×Ecri≧2×α×BV, Ecri=2.0 to 3.0×10 5 [V/cm], α=10 0 to 10 1 . Widths of the P-type ring layers of the plurality of units linearly decrease toward an outside of the termination region.
1. A semiconductor device maintaining a withstand voltage which is equal to or higher than a target withstand voltage, wherein a silicon substrate is provided with an active region in which a transistor is formed and a termination region located around the active region,
the termination region includes a ring region,
a plurality of ring-shaped P-type ring layers are regularly arranged in the ring region,
the ring region is divided into a plurality of units which include the plurality of ring-shaped P-type ring layers respectively,
a width of each unit is constant,
a total number of P-type impurities in the ring region is N, the target withstand voltage is BV [V], a width of each unit is SandL [μm], and the number of the plurality of units is num, following relationships are satisfied,
N ≧( M×BV ) γ ,M= 10 4 to 10 5 ,γ=0.55 to 1.95,
SandL ×num× Ecri≧ 2×α× BV,
Ecri= 2.0 to 3.0×10 5 [V/cm],α=10 0 to 10 1 ,and
widths of the plurality of ring-shaped P-type ring layers of the plurality of units linearly decrease toward an outside of the termination region.
2. The semiconductor device according to claim 1 , wherein the plurality of ring-shaped P-type ring layers include a plurality of striped structures regularly arranged in a plan view.
3. The semiconductor device according to claim 1 , wherein the plurality of ring-shaped P-type ring layers include a plurality of dotted structures regularly arranged in a plan view.
4. The semiconductor device according to claim 1 , wherein the termination region further includes a P-type layer that overlaps with at least part of the ring region,
a surface concentration of the P-type layer is smaller than a surface concentration of the plurality of ring-shaped P-type ring layers, and
a depth of the P-type layer is greater than a depth of the plurality of ring-shaped P-type ring layers.
5. A semiconductor device maintaining a withstand voltage which is equal to or higher than a target withstand voltage, wherein a silicon substrate is provided with an active region in which a transistor is formed and a termination region located around the active region,
the termination region includes a plurality of ring regions,
a plurality of ring-shaped P-type ring layers are regularly arranged in each ring region,
each ring region is divided into a plurality of units which include the plurality of ring-shaped P-type ring layers respectively,
a width of each unit is constant within the same ring region,
a total number of P-type impurities in an i-th ring region among the plurality of ring regions is N(i), the target withstand voltage is BV [V], a withstand voltage supported by the i-th ring region is BV(i) [V], width of each unit of the i-th ring region is SandL(i) [μm], and the number of the plurality of units in the i-th ring region is num(i), following relationships are satisfied,
N ( i )≧( M×BV ( i )) γ ,M= 10 4 to 10 5 ,γ=0.55 to 1.95,
Σ[ SandL ( i )×num( i )× E max( i )]≧2×α× BV,
BV=ΣBV ( i ), E max( i )≦ Ecri,Ecri= 2.0 to 3.0×10 5 [V/cm],α=10 0 to 10 1 ,and
widths of the plurality of ring-shaped P-type ring layers of the plurality of units linearly decrease toward an outside of the termination region.
6. The semiconductor device according to claim 5 , wherein the plurality of ring-shaped P-type ring layers include a plurality of striped structures regularly arranged in a plan view.
7. The semiconductor device according to claim 5 , wherein the plurality of ring-shaped P-type ring layers include a plurality of dotted structures regularly arranged in a plan view.
8. The semiconductor device according to claim 5 , wherein the termination region further includes a P-type layer that overlaps with at least part of the ring region,
a surface concentration of the P-type layer is smaller than a surface concentration of the plurality of ring-shaped P-type ring layers, and
a depth of the P-type layer is greater than a depth of the plurality of ring-shaped P-type ring layers.