IP Library › Granted Patent US 9,385,222
Granted Patent B2
US 9,385,222 · App. 14/180,924 · Granted Jul 5, 2016

Semiconductor device with insert structure at a rear side and method of manufacturing

Inventors: Johannes Georg Laven (Taufkirchen, DE); Hans-Joachim Schulze (Taufkirchen, DE); Anton Mauder (Kolbermoor, DE); Erich Griebl (Dorfen, DE)
Assignee: Infineon Technologies AG
H01L29/7395H01L21/0265H01L21/02532H01L21/02595H01L21/02598H01L21/02636H01L21/02639H01L21/02642H01L21/02667H01L21/2251H01L21/2254H01L21/2257H01L21/26513H01L21/30604H01L21/324H01L21/3247H01L21/6835H01L29/04H01L29/0634H01L29/0649H01L29/0696H01L29/1095H01L29/16H01L29/36H01L29/66333H01L21/26533H01L23/544H01L2221/6834H01L2221/68327H01L2223/5446H01L2223/54426
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Quick Facts
Patent No.
US 9,385,222
App. No.
14/180,924
Granted
Jul 5, 2016
Kind
B2
Abstract

A cavity is formed in a first semiconductor layer that is formed on a semiconducting base layer. The cavity extends from a process surface of the first semiconductor layer to the base layer. A recessed mask liner is formed on a portion of a sidewall of the cavity distant to the process surface or a mask plug is formed in a portion of the cavity distant do the process surface. A second semiconductor layer is grown by epitaxy on the process surface. The second semiconductor layer spans the cavity.

Claims (9)

1. A method of manufacturing a semiconductor device, the method comprising:

forming a cavity in a first semiconductor layer formed on a semiconducting base layer, wherein the cavity extends from a process surface of the first semiconductor layer at least down to the base layer;

forming a recessed mask liner on a portion of a sidewall of the cavity distant to the process surface or a mask plug in a portion of the cavity distant to the process surface; capping the cavity by annealing the first semiconductor layer in a hydrogen-containing ambient before growing the second semiconductor layer, wherein material of the first semiconductor layer occludes the cavity; and

growing a second semiconductor layer on the process surface by epitaxy, wherein the second semiconductor layer spans the cavity.

2. The method of claim 1 , further comprising:

forming an auxiliary pad on a first section of a surface of the semiconducting base layer, the auxiliary pad adapted to suppress an epitaxial growth; and

selectively growing by epitaxy the first semiconductor layer on a second section of the surface, wherein the cavity is formed in a vertical projection of the auxiliary pad.

3. The method of claim 1 , further comprising:

removing at least a portion of the base layer after growing the second semiconductor layer, wherein the cavity or a material in the cavity is exposed.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 5, 2014
From: LAVEN, JOHANNES GEORG; SCHULZE, HANS-JOACHIM; MAUDER, ANTON; GRIEBL, ERICH
To: INFINEON TECHNOLOGIES AG
Reel/Frame 032821/0919 →
Continuity (1)
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