Chip and method for manufacturing a chip
According to one embodiment, a chip is described comprising a plurality of supply lines delimiting a plurality of cell areas and a gate comprising a first transistor and a second transistor, wherein the first transistor is located in a first cell area of the plurality of cell areas and the second transistor is located in a second cell area of the plurality of cell areas such that a supply line of the plurality of supply lines lies between the first cell area and the second cell area.
1. A chip comprising:
a plurality of supply lines delimiting a plurality of cell areas; and
a split gate comprising a first transistor and a second transistor, wherein the first transistor is located in a first cell row of the plurality of cell rows and the second transistor is located in a second cell row of the plurality of cell rows such that a supply line of the plurality of supply lines lies between the first cell row and the second cell row; and wherein the first transistor is directly connected to the second transistor.
2. The chip according to claim 1 , wherein the split gate is a Boolean or a sequential gate.
3. The chip according to claim 1 , wherein the split gate is a complex gate.
4. The chip according to claim 1 , wherein the split gate implements a basic Boolean function.
5. The chip according to claim 4 , wherein the basic Boolean function is a Boolean NOT, a Boolean AND, a Boolean OR, a Boolean NAND, a Boolean NOR, a Boolean EXOR or a Boolean EXNOR.
6. The chip according to claim 1 , wherein the transistors are field effect transistors.
7. The chip according to claim 1 , wherein the first transistor and the second transistor are both p channel field effect transistors or are both n channel field effect transistors.
8. The chip according to claim 1 , wherein the split gate is implemented in CMOS technology.
9. The chip according to claim 1 , wherein the split gate comprises a multiplicity of transistors, wherein a first subset of the multiplicity of transistors is located in the first cell row and a second subset of the multiplicity of transistors is located in the second cell row.
10. The chip according to claim 9 , wherein the first subset and the second subset both include both at least one n channel field effect transistor and at least one p channel field effect transistor.
11. The chip according to claim 1 , wherein the supply lines of the plurality of supply lines are arranged substantially in parallel to each other.
12. The chip according to claim 11 , wherein the plurality of supply lines alternately comprises a supply line for a high supply potential and a supply line for a low supply potential.
13. The chip according to claim 1 , wherein each cell row is limited at one side by a supply line for a high supply potential and on another side by a supply line for a low supply potential.
14. The chip according to claim 1 , wherein the split gate occupies only a half of the first cell row or only a half of the second cell row according to a horizontal splitting of the cell rows into halves.
15. The chip according to claim 1 , comprising a multiplicity of supply lines delimiting a multiplicity of cell rows; and
a multiplicity of split gates, each split gate comprising a first transistor and a second transistor, wherein the first transistor is located in a first cell row of the multiplicity of cell rows and the second transistor is located in a second cell row of the multiplicity of cell rows such that a supply line of the multiplicity of supply lines lies between the first cell row and the second cell row; and wherein the first transistor and the second transistor are directly connected within each split gate.
16. The chip according to claim 15 , wherein the multiplicity of split gates is connected to form an integrated circuit.
17. The chip according to claim 15 , further comprising one or more further split gates which each lie within one cell row of the multiplicity of cell rows.
18. The chip according to claim 17 , wherein the multiplicity of split gates and the one or more further gates are connected to form an integrated circuit.
19. The chip according to claim 1 , wherein the direct connection between the first transistor and the second transistor is a serial connection or a parallel connection.
20. The chip according to claim 1 , wherein the serial connection comprises a drain of the first transistor connected to a source of the second transistor or a source of the first transistor connected to a drain of the second transistor; and wherein the parallel connection comprises a source of the first gate connected to a source of the second gate and a drain of the first gate connected to a drain of the second gate.