Source/drain structure and manufacturing the same

1. A device comprising:

a semiconductor substrate having a source/drain region;

a plurality of isolation regions over the semiconductor substrate; and

a source/drain feature in the source/drain region, the source/drain feature including:

multiple plug-type portions over the substrate, wherein each of the plug-type portions is isolated from each other by a respective isolation region; and

a single upper portion over the isolation regions, wherein the single upper portion is merged from the multiple plug-type portions, wherein the single upper portion has a top surface facing away from a top surface of the isolation regions, wherein the top surface of the single upper portion includes a first flat surface connected to a multi-facet surface and a second flat surface connected to the multi-facet surface.

2. The device of claim 1 , wherein the single upper portion having the top surface is such that a ratio of the lowest height to the highest height of the single upper portion of the semiconductor feature is more than about 90%.

3. The device of claim 1 , wherein a height of the plug-type portion of the source/drain feature is larger than about 10 nm.

4. The device of claim 1 , wherein the source/drain feature includes epitaxial silicon germanium (SiGe).

5. The device of claim 1 , further includes:

a gate region adjacent to the source/drain region;

a plurality of fin feature in the gate region, wherein the plurality of fin features physically contact the same single upper portion of the source/drain feature; and

gate stacks disposed over the substrate, including wrapping over the respective fin feature.

6. The device of claim 1 , further includes a semiconductor layer wraps over the source/drain feature, wherein the semiconductor layer has a different semiconductor material than the source/drain feature.

7. The device of claim 1 , wherein the plug-type portions of the S/D feature physically contact the substrate.

8. A fin-like field-effect transistor (FinFET) device comprising:

a substrate having a source/drain (S/D) region;

a plurality of isolation regions over the substrate; and

a silicon germanium (SiGe) S/D feature in the source/drain region, the SiGe S/D feature including:

multiple plug-type portions over the substrate, wherein each plug-type portion is embedded in an isolation region; and

a single upper portion over the isolation region, wherein the single upper portion is merged from the multiple plug-type portions, wherein the single upper portion has a top surface, facing away from a top surface of the isolation region, having a flat surface connects with a multi-facet surface in a repetitive manner.

9. The device of claim 8 , wherein the multi-facet surface is aligned to the respective plug-type portion.

10. The device of claim 8 , wherein the multi-facet surface includes two facets, wherein:

each of two facets has a fix angle with the flat surface;

one of two facets starts from the flat surface and meets an end of the another facet which also starts from the flat surface.

11. The device of claim 10 , wherein a ratio of a distance between the end where two facets meet and a top surface of the isolation region 230 to a distance between the flat surface and a top surface of the isolation region is more than about 90%.

12. The device of claim 10 , wherein the two facets has (111) crystal plane orientation.

13. The device of claim 8 , further includes:

a gate region adjacent to the source/drain regions;

a plurality of fin feature in the gate region, wherein the plurality of fin features physically contact the same single upper portion of the SiGe S/D feature; and

gate stacks disposed over the substrate, including wrapping over the respective fin feature.

14. The device of claim 8 , wherein the plug-type portion of the SiGe S/D feature physically contact the substrate.

15. The device of claim 8 , wherein a height of the plug-type portion of the SiGe S/D feature is larger than about 10 nm.

16. The device of claim 8 , further includes a semiconductor layer over the semiconductor feature, wherein the semiconductor layer has a different semiconductor material than the semiconductor feature.

17. A device comprising:

a semiconductor substrate having a source/drain region;

a plurality of isolation regions over the semiconductor substrate; and

a source/drain feature in the source/drain region, the source/drain feature including:

three plug-type portions over the substrate, wherein the plug-type portions are isolated from each other by two isolation regions; and

a single upper portion over the two isolation regions, wherein the single upper portion is merged from the three plug-type portions, wherein the single upper portion has a top surface facing away from a top surface of the isolation regions, wherein the top surface of the single upper portion includes a first flat surface connected to a multi-facet surface and a second flat surface connected to the multi-facet surface.

18. The device of claim 17 , wherein the single upper portion having the top surface is configured such that a ratio of the lowest height to the highest height of the single upper portion of the semiconductor feature is more than about 90%.

19. The device of claim 17 , wherein a height of the plug-type portions of the source/drain feature is larger than about 10 nm.

20. The device of claim 17 , wherein the source/drain feature includes epitaxial silicon germanium (SiGe).