IP Library › Granted Patent US 9,397,059
Granted Patent B2
US 9,397,059 · App. 14/840,811 · Granted Jul 19, 2016

Bonded structures for package and substrate

Inventors: Ming-Hong Cha (Hsin-Chu, TW); Chen-Shien Chen (Zhubei, TW); Chen-Cheng Kuo (Chu-Pei, TW); Tsung-Hsien Chiang (Hsin-Chu, TW); Hao-Juin Liu (Kaohsiung, TW); Yao-Chun Chuang (Hsin-Chu, TW); Chita Chuang (Hsin-Chu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L24/13H01L21/76897H01L24/11H01L24/14H01L24/16H01L23/49816H01L23/49827H01L23/49838H01L24/17H01L24/81H01L25/0657H01L2224/0401H01L2224/05022H01L2224/05124H01L2224/05144H01L2224/05147H01L2224/05166H01L2224/05181H01L2224/05186H01L2224/05572H01L2224/05647H01L2224/05666H01L2224/05681H01L2224/05686H01L2224/131H01L2224/13014H01L2224/13082H01L2224/13083H01L2224/13124H01L2224/13139H01L2224/13144H01L2224/13147H01L2224/13166H01L2224/13601H01L2224/141H01L2224/145H01L2224/14154H01L2224/14177H01L2224/16238H01L2224/171H01L2224/814H01L2224/81193H01L2224/81815H01L2225/06513H01L2924/00014H01L2924/01029H01L2924/1305H01L2924/13091H01L2924/3511H01L2924/3841
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Quick Facts
Patent No.
US 9,397,059
App. No.
14/840,811
Granted
Jul 19, 2016
Kind
B2
Abstract

The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.

Claims (29)

1. A semiconductor device comprising:

a first contact post with a first elongated shape, a first sidewall, and a second sidewall opposite the first sidewall; and

an opening within a passivation layer, the opening exposing an underlying conductive region over a substrate, the opening having a third sidewall and a fourth sidewall opposite the third sidewall, wherein the third sidewall and the fourth sidewall enclose a central region and wherein the first sidewall is directly over the central region and the second sidewall is offset from the central region in a direction parallel with a major surface of the substrate, wherein the first contact post is in electrical connection with the conductive region.

2. The semiconductor device of claim 1 , further comprising a reflowable material electrically connecting the first contact post to the conductive region.

3. The semiconductor device of claim 2 , wherein the reflowable material wets the first sidewall but does not wet the second sidewall.

4. The semiconductor device of claim 2 , wherein the reflowable material extends into the central region.

5. The semiconductor device of claim 1 , further comprising a second contact post with a second elongated shape, wherein the first elongated shape has a first longitudinal axis and the second elongated shape has a second longitudinal axis parallel with the first longitudinal axis.

6. The semiconductor device of claim 5 , further comprising a third contact post with a third elongated shape, wherein the third elongated shape has a third longitudinal axis that is not parallel with the first longitudinal axis.

7. The semiconductor device of claim 1 , further comprising a second contact post with a second elongated shape, wherein the first elongated shape has a first longitudinal axis and the second elongated shape has a second longitudinal axis, wherein the first longitudinal axis and second longitudinal axis are both aligned to cross a center of the semiconductor device.

8. A semiconductor device comprising:

a first conductive post on a die package; and

a solder layer, the solder layer being in physical contact with a metal pad over a substrate, wherein a surface of the first conductive post facing a center of the die package is not wetted by the solder layer, and wherein a surface of the first conductive post not facing the center of the die package is wetted by the solder layer.

9. The semiconductor device of claim 8 , further comprising a second conductive post on the die package, wherein the first conductive post has a first longitudinal axis and the second conductive post has a second longitudinal axis, wherein the first longitudinal axis and the second longitudinal axis are parallel with each other.

10. The semiconductor device of claim 9 , further comprising a third conductive post with a third longitudinal axis, wherein the first longitudinal axis is aligned with the second longitudinal axis, wherein the first longitudinal axis has a first intersection point with a first perimeter of the first conductive post, the third longitudinal axis has a second intersection point with a second perimeter of the third conductive post, wherein the first intersection point is the closest intersection point within the first conductive post to the second intersection point, and wherein a line extending from the first intersection point to the second intersection point has an angle with the first longitudinal axis of between about 30° and 60°.

11. The semiconductor device of claim 8 , wherein a surface of the first conductive post not facing the center of the die package is located directly over a passivation layer, the passivation layer comprising an opening at least partially filled with a reflowable material.

12. The semiconductor device of claim 11 , wherein the opening has an elongated shape.

13. The semiconductor device of claim 8 , wherein the first conductive post comprises copper.

14. The semiconductor device of claim 8 , further comprising a second conductive post on the die package, wherein the first conductive post has a first longitudinal axis and the second conductive post has a second longitudinal axis, wherein the first longitudinal axis and the second longitudinal axis are both aligned with the center of the die package.

15. A semiconductor device comprising:

a first contact post on a first package;

a conductive region over a first substrate;

a passivation layer over the first substrate;

an opening through the passivation layer, wherein the opening is laterally offset from the first contact post in a direction parallel with a major surface of the first substrate; and

a reflowable material extending from the opening to the first contact post, wherein the reflowable material electrically connects the first contact post to the conductive region, wherein the reflowable material is in contact with a first sidewall of the first contact post but not in contact with a second sidewall of the first contact post.

16. The semiconductor device of claim 15 , wherein the first contact post has a first elongated shape.

17. The semiconductor device of claim 16 , wherein the opening has a second elongated shape.

18. The semiconductor device of claim 16 , further comprising a second contact post having a second elongated shape, wherein the first contact post has a first longitudinal axis parallel with a second longitudinal axis of the second contact post.

19. The semiconductor device of claim 18 , wherein a pitch between the first contact post and the second contact post is between about 20 μm and about 200 μm.

20. The semiconductor device of claim 18 , wherein a line extending from a first top of the first contact post to a second tip of the second contact post is at an angle to the first longitudinal axis of the first contact post of between about 30° and about 60°.

Continuity (4)
Continuation 14480439 · Sep 8, 2014
Continuation 13667306 · Nov 2, 2012
Provisional Application 61684565 · Aug 17, 2012
Related Publication 20150371964A1 · Dec 24, 2015