IP Library Granted Patent US 9,397,156
Granted Patent B2
US 9,397,156 · App. 14/951,124 · Granted Jul 19, 2016

Semiconductor device and method of manufacturing the same

Inventor: Tsuyoshi Kachi (Kanagawa, JP)
Assignee: Renesas Electronics Corporation
H01L29/0634H01L21/225H01L21/26586H01L21/324H01L29/0619H01L29/66734
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Quick Facts
Patent No.
US 9,397,156
App. No.
14/951,124
Granted
Jul 19, 2016
Kind
B2
Abstract

To realize a semiconductor device having a power MOSFET satisfying both a low conduction resistance and a high junction breakdown voltage by a simple and easy manufacturing method. Over an n-type substrate, a p-type epitaxial layer of a low concentration is formed, and, in an active part, a plurality of active regions is defined by a plurality of trenches that is formed in the epitaxial layer and extends in a first direction with first intervals in a second direction orthogonal to the first direction. In the epitaxial layer between the adjacent trenches, an n-type diffusion region that functions as a drain offset layer is formed, and, in the epitaxial layer between a side wall of the trench and the n-type diffusion region, a p-type diffusion region connected with a channel region (the p-type diffusion region) is formed, to constitute a super junction structure. Further, by forming an n-type diffusion region in the epitaxial layer, having a prescribed width from a side wall of a trench lying in the end part of the active part toward an outer periphery part, to achieve the improvement of a drain breakdown voltage.

Claims (8)

1. A method of manufacturing a semiconductor device including an active part in which a power MOSFET is formed and an outer peripheral part formed around the active part, comprising the steps of:

(a) forming, over a substrate of a first conductivity type, an epitaxial layer of a second conductivity type different from the first conductivity type;

(b) forming, in the epitaxial layer in the active part, a plurality of first trenches, each of which has a first depth from an upper face of the epitaxial layer, and which extends in a first direction in plan view with a first interval provided therebetween in a second direction orthogonal to the first direction in plan view;

(c) after the step (b), inclinedly ion-implanting a first impurity ion of the first conductivity type into the epitaxial layer from a side wall of the first trench;

(d) after the step (c), providing a heat treatment to diffuse the first impurity ion into the whole of the epitaxial layer between the adjacent first trenches;

(e) after the step (d), inclinedly ion-implanting a second impurity ion of the second conductivity type into the epitaxial layer from a side wall of the first trench;

(f) after the step (e), providing a heat treatment to diffuse the second impurity ion so as not to spread into the whole of the epitaxial layer between the adjacent first trenches; and

(g) after the step (f), embedding a first insulating film inside the first trench.

Assignments (1)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
Priority Claims (1)
JP 2013-020722 · Feb 5, 2013 · national
Continuity (2)
Division 14149908 · Jan 8, 2014
Related Publication 20160079352A1 · Mar 17, 2016