Solid-state imaging device having an enlarged dynamic range, and electronic system
A solid-state imaging device includes: a pixel array including a plurality of pixels disposed in a matrix, the pixels including a charge holding section configured to hold a signal charge transferred from a photoelectric conversion section, and to include a capacitor section having a first capacitance value and an additional capacitor section for increasing the first capacitance value to be a second capacitance value; and to part of a reset transistor configured to reset a charge held by the charge holding section, a test-voltage power source configured to apply a test voltage having a voltage different from a drive voltage of the reset transistor.
1. A solid-state imaging device comprising:
a pixel array including a plurality of pixels disposed in a matrix, the plurality of pixels including a charge holding section configured to hold a signal charge transferred from a photoelectric conversion section, and a capacitor section having a first capacitance value and an additional capacitor section for increasing the first capacitance value to be a second capacitance value;
a reset transistor configured to reset a charge held by the charge holding section;
a test-voltage power source configured to apply a test voltage having a voltage different from a drive voltage of the reset transistor; and
a calculation section configured to calculate a capacitance ratio being a ratio of the first capacitance value to the second capacitance value on the basis of a high gain signal generated on the basis of a signal voltage corresponding to a charge stored in the charge holding section in an event capacity of the charge holding section is set to the first capacitance value, and a low gain signal generated on the basis of a signal voltage in an event capacity of the charge holding section is set to the second capacitance value.
2. The solid-state imaging device according to claim 1 ,
wherein in each of the plurality of pixels in the pixel array,
before a pixel signal corresponding to light received by the photoelectric conversion section is read, the reset transistor is turned on so that the charge holding section holds a charge corresponding to the test voltage.
3. The solid-state imaging device according to claim 1 ,
wherein in pixels in one predetermined row in the pixel array,
before a pixel signal corresponding to light received by the photoelectric conversion section is read, the reset transistor is turned on so that the charge holding section holds a charge corresponding to the test voltage.
4. The solid-state imaging device according to claim 3 ,
wherein a light receiving section of the pixels in the one predetermined row in the pixel array is shaded, and
before the pixel signal corresponding to the light received by the photoelectric conversion section is read, a transfer transistor configured to transfer a signal charge from the photoelectric conversion section to the charge holding section is turned on together with the reset transistor so that the photoelectric conversion section holds a charge corresponding to the test voltage.
5. The solid-state imaging device according to claim 1 ,
wherein each of the high gain signal and the low gain signal is a signal from which noise has been removed by correlated double sampling processing.
6. The solid-state imaging device according to claim 1 , further comprising a memory configured to store the capacitance ratio.
7. An electronic system comprising:
a solid-state imaging device including
a pixel array including a plurality of pixels disposed in a matrix, the plurality of pixels including a charge holding section configured to hold a signal charge transferred from a photoelectric conversion section, and a capacitor section having a first capacitance value and an additional capacitor section for increasing the first capacitance value to be a second capacitance value;
a reset transistor configured to reset a charge held by the charge holding section;
a test-voltage power source configured to apply a test voltage having a voltage different from a drive voltage of the reset transistor; and
a calculation section configured to calculate a capacitance ratio being a ratio of the first capacitance value to the second capacitance value on the basis of a high gain signal generated on the basis of a signal voltage corresponding to a charge stored in the charge holding section in an event capacity of the charge holding section is set to the first capacitance value, and a low gain signal generated on the basis of a signal voltage in an event capacity of the charge holding section is set to the second capacitance value.