Cells having transistors and interconnects including nanowires or 2D material strips
An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a plurality of transistors and an interconnect; wherein a transistor in the plurality has a channel comprising one or more nanowires or 2D material strips arranged in parallel, and the interconnect comprises one or more nanowires or 2D material strips arranged in parallel and connected to terminals of more than one of the transistors in the plurality of transistors. An integrated circuit including the plurality of transistors and the interconnect is described.
1. A computer system adapted to process a computer implemented representation of a circuit design, comprising:
a processor and memory coupled to the processor, the memory storing instructions executable by the processor, including instructions to select cells from a cell library;
the cell library including entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language; and
at least one entry in the cell library comprising a specification of a cell including
a plurality of transistors and an interconnect; wherein
a transistor in the plurality has a channel comprising one or more nanowires or 2D material strips arranged in parallel, and the interconnect comprises one or more nanowires or 2D material strips arranged in parallel and connected to terminals of more than one of the transistors in the plurality of transistors.
2. The computer system of claim 1 , wherein nanowires or 2D material strips in the nanowires or 2D material strips of the interconnect include segments disposed horizontally relative to a surface of a substrate, and nanowires or 2D material strips of the transistor are disposed vertically relative to the surface of the substrate.
3. The computer system of claim 1 , wherein nanowires or 2D material strips in the one or more nanowires or 2D material strips of the interconnect include segments disposed vertically relative to a surface of a substrate, and the nanowires or 2D material strips in the one or more nanowires or 2D material strips of the transistor are disposed horizontally to the surface of the substrate.
4. The computer system of claim 1 , wherein nanowires or 2D material strips in the one or more nanowires or 2D material strips of the interconnect include segments disposed horizontally relative to a surface of a substrate, and nanowires or 2D material strips in the one or more nanowires or 2D material strips of the transistor are horizontally relative to the surface of the substrate.
5. The computer system of claim 1 , wherein said interconnect connects a gate terminal of one transistor in the plurality to a source or drain terminal of another transistor in the plurality.
6. The computer system of claim 1 , wherein nanowires or 2D material strips in one of the interconnect and the transistor include nanowires or 2D material strips disposed in a stack having a number of layers.
7. The computer system of claim 1 , wherein nanowires or 2D material strips in one of the interconnect and the transistor include nanowires or 2D material strips disposed in a plurality of stacks.
8. The computer system of claim 1 , wherein nanowires or 2D material strips in the one or more nanowires or 2D material strips of the interconnect include segments disposed above the nanowires or 2D material strips in the one or more nanowires or 2D material strips of the transistor.
9. The computer system of claim 1 , wherein nanowires or 2D material strips in the one or more nanowires or 2D material strips of the interconnect include segments disposed below the nanowires or 2D material strips in the one or more nanowires or 2D material strips of the transistor.
10. The computer system of claim 1 , wherein nanowires or 2D material strips in one of the interconnect and the transistor include a nanowire having a minimum dimension which is less than 10 nanometers.
11. The computer system of claim 1 , wherein
the instructions further include logic to utilize the specification in said at least one entry to determine a physical placement of the cell.
12. A computer program product, comprising:
a memory including non-transitory computer-readable media having stored thereon a cell library including entries for a plurality of cells, entries in the cell library including a machine readable specification of a cell, the specification of the cell including computer readable parameters specifying structural features of a physical implementation of a circuit, the specification of the cell being executable by a computer using the computer readable parameters stored on the non-transitory computer-readable media to run a placement process to control physical placement of the circuit with other circuits or components, the circuit including:
a plurality of transistors and an interconnect, wherein:
a transistor in the plurality has a channel comprising one or more nanowires or 2D material strips arranged in parallel, and the interconnect comprises one or more nanowires or 2D material strips arranged in parallel and connected to terminals of more than one of the transistors in the plurality of transistors.
13. The computer program product of claim 12 , wherein nanowires or 2D material strips in the nanowires or 2D material strips of the interconnect include segments disposed horizontally relative to a surface of a substrate, and nanowires or 2D material strips of the transistor are disposed vertically relative to the surface of the substrate.
14. The computer program product of claim 12 , wherein nanowires or 2D material strips in the one or more nanowires or 2D material strips of the interconnect include segments disposed vertically relative to a surface of a substrate, and the nanowires or 2D material strips in the one or more nanowires or 2D material strips of the transistor are disposed horizontally to the surface of the substrate.
15. The computer program product of claim 12 , wherein nanowires or 2D material strips in the one or more nanowires or 2D material strips of the interconnect include segments disposed horizontally relative to a surface of a substrate, and nanowires or 2D material strips in the one or more nanowires or 2D material strips of the transistor are horizontally relative to the surface of the substrate.
16. The computer program product of claim 12 , wherein said interconnect connects a gate terminal of one transistor in the plurality to a source or drain terminal of another transistor in the plurality.
17. The computer program product of claim 12 , wherein nanowires or 2D material strips in one of the interconnect and the transistor include nanowires or 2D material strips disposed in a stack having a number of layers.
18. The computer program product of claim 12 , wherein nanowires or 2D material strips in one of the interconnect and the transistor include nanowires or 2D material strips disposed in a plurality of stacks.
19. The computer program product of claim 12 , wherein nanowires or 2D material strips in the one or more nanowires or 2D material strips of the interconnect include segments disposed above the nanowires or 2D material strips in the one or more nanowires or 2D material strips of the transistor.
20. The computer program product of claim 12 , wherein nanowires or 2D material strips in the one or more nanowires or 2D material strips of the interconnect include segments disposed below the nanowires or 2D material strips in the one or more nanowires or 2D material strips of the transistor.
21. The computer program product of claim 12 , wherein nanowires or 2D material strips in one of the interconnect and the transistor include a nanowire having a minimum dimension which is less than 10 nanometers.