IP Library Granted Patent US 9,405,541
Granted Patent B2
US 9,405,541 · App. 13/422,550 · Granted Aug 2, 2016

Run-time instrumentation indirect sampling by address

Inventors: Jonathan D. Bradbury (Poughkeepsie, NY); Charles W. Gainey, Jr. (Poughkeepsie, NY); Michael K. Gschwind (Chappaqua, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
G06F9/30076G06F11/348G06F11/3636G06F11/3648G06F2201/86G06F2201/87
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,405,541
App. No.
13/422,550
Granted
Aug 2, 2016
Kind
B2
Abstract

The invention relates to implementing run-time instrumentation indirect sampling by address. An aspect of the invention includes a method for implementing run-time instrumentation indirect sampling by address. The method includes reading sample-point addresses from a sample-point address array, and comparing, by a processor, the sample-point addresses to an address associated with an instruction from an instruction stream executing on the processor. The method further includes recognizing a sample point upon execution of the instruction associated with the address matching one of the sample-point addresses. Run-time instrumentation information is obtained from the sample point. The method also includes storing the run-time instrumentation information in a run-time instrumentation program buffer as a reporting group.

Claims (51)

1. A computer program product for implementing run-time instrumentation indirect sampling by address, the computer program product comprising:

a tangible non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:

initializing a run-time-instrumentation control based on executing a load run-time instrumentation controls (LRIC) instruction, the LRIC instruction establishing a sampling mode and a sample-point address (SPA) control according to a sampling control block included as an operand of the LRIC instruction, the sampling mode selectable to enable an indirect sampling by address mode in combination with a directed sampling mode that triggers sampling upon execution of a next sequential instruction following a run-time instrumentation next instruction, and/or an interval-based sampling mode that triggers sampling at specified intervals;

collecting into a collection buffer that is internal to a processor, a plurality of run-time instrumentation information comprising events and data associated with execution of an instruction stream while the instruction stream is executing on the processor;

reading sample-point addresses from a sample-point address array in a register that is internal to the processor;

comparing, by the processor, the sample-point addresses to an address associated with an instruction from an instruction stream executing on the processor;

recognizing a sample point upon execution of the instruction associated with the address matching one of the sample-point addresses, wherein run-time instrumentation information is obtained from the sample point; and

triggering a transfer of the run-time instrumentation information from the collection buffer to a run-time instrumentation program buffer as a reporting group based on recognizing the sample point, wherein the run-time instrumentation program buffer is located in memory that is external to the processor.

2. The computer program product of claim 1 , wherein the address associated with the instruction, based on address type, is one of: an address of the instruction and an address of an operand of the instruction.

3. The computer program product of claim 1 , wherein initializing the run-time-instrumentation control based on executing the LRIC instruction further comprises establishing a sample-point address type as one of: an instruction address and an address of an operand of an instruction.

4. The computer program product of claim 1 , further comprising:

fetching a run-time instrumentation load sample point addresses (RILSPA) instruction comprising the sample-point addresses; and

executing the RILSPA instruction by the processor, the executing comprising:

storing the sample-point addresses in the sample-point address array; and

updating a condition code in the processor based on the storing.

5. The computer program product of claim 4 , further comprising:

performing an address translation on the sample-point addresses based on a dynamic address translation state prior to storing the sample-point addresses in the sample-point address array.

6. The computer program product of claim 1 , further comprising:

fetching a run-time instrumentation store sample point addresses (RISSPA) instruction comprising a storage address; and

executing the RISSPA instruction by the processor, the executing comprising:

reading the sample-point addresses from the sample-point address array; and

storing the sample-point addresses to a location identified by the storage address.

7. The computer program product of claim 1 , further comprising:

fetching a run-time instrumentation clear sample point addresses (RICSPA) instruction; and

executing the RICSPA instruction by the processor, the executing comprising:

clearing the sample-point addresses in the sample-point address array; and

updating a condition code in the processor based on the clearing.

8. A system for implementing run-time instrumentation indirect sampling by address, the system comprising:

a memory; and

a processor comprising a run-time instrumentation module, the run-time instrumentation module configured to perform a method comprising:

initializing a run-time-instrumentation control based on executing a load run-time instrumentation controls (LRIC) instruction, the LRIC instruction establishing a sampling mode and a sample-point address (SPA) control according to a sampling control block included as an operand of the LRIC instruction, the sampling mode selectable to enable an indirect sampling by address mode in combination with a directed sampling mode that triggers sampling upon execution of a next sequential instruction following a run-time instrumentation next instruction, and/or an interval-based sampling mode that triggers sampling at specified intervals;

collecting into a collection buffer that is internal to the processor, a plurality of run-time instrumentation information comprising events and data associated with execution of an instruction stream while the instruction stream is executing on the processor;

reading sample-point addresses from a sample-point address array in a register that is internal to the processor;

comparing, by the processor, the sample-point addresses to an address associated with an instruction from an instruction stream executing on the processor;

recognizing a sample point upon execution of the instruction associated with the address matching one of the sample-point addresses, wherein run-time instrumentation information is obtained from the sample point; and

triggering a transfer of the run-time instrumentation information from the collection buffer to a run-time instrumentation program buffer as a reporting group based on recognizing the sample point, wherein the run-time instrumentation program buffer is located in memory that is external to the processor.

9. The system of claim 8 , further comprising:

fetching a run-time instrumentation load sample point addresses (RILSPA) instruction comprising the sample-point addresses; and

executing the RILSPA instruction by the processor, the executing comprising:

storing the sample-point addresses in the sample-point address array; and

updating a condition code in the processor based on the storing.

10. The system of claim 8 , further comprising:

fetching a run-time instrumentation store sample point addresses (RISSPA) instruction comprising a storage address; and

executing the RISSPA instruction by the processor, the executing comprising:

reading the sample-point addresses from the sample-point address array; and

storing the sample-point addresses to a location identified by the storage address.

11. The system of claim 8 , further comprising:

fetching a run-time instrumentation clear sample point addresses (RICSPA) instruction; and

executing the RICSPA instruction by the processor, the executing comprising:

clearing the sample-point addresses in the sample-point address array; and

updating a condition code in the processor based on the clearing.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE ADDRESS OF THE ASSIGNEE FROM ARMOND, NY TO ARMONK, NY 10504 PREVIOUSLY RECORDED ON REEL 028049 FRAME 0880. ASSIGNOR(S) HEREBY CONFIRMS THE ADDRESS OF THE ASSIGNEE TO BE INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW ORCHARD ROAD, ARMONK, NY 10504. Recorded Apr 27, 2012
From: BRADBURY, JONATHAN D.; GAINEY, CHARLES W., JR.; GSCHWIND, MICHAEL K.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 028117/0650 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2012
From: BRADBURY, JONATHAN D.; GAINEY, CHARLES W., JR.; GSCHWIND, MICHAEL K.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 028049/0880 →
Continuity (1)
Related Publication 20130246754A1 · Sep 19, 2013