Workload adaptive address mapping
Embodiments of the invention describe an apparatus, system and method for workload adaptive address mapping. Embodiments of the invention may receive a request to initialize a system memory including a plurality of memory banks. Using a plurality of memory address mapping schemes for memory settings for the system memory, a system characterization workload is executed during the initialization of the system memory, the system characterization workload including a plurality of transactions directed towards the system memory. Embodiments of the invention may monitor target addresses of the plurality of transactions directed towards the system memory. One of the plurality of memory address mapping schemes is selected based, at least in part, on the target addresses of the plurality of transactions.
1. A method comprising:
receiving a request to initialize a system memory including a plurality of memory banks; and
during the initialization of the system memory:
executing, using a plurality of memory address mapping schemes for memory settings for the system memory, a system characterization workload including a plurality of transactions directed towards the system memory, by monitoring target addresses of the plurality of transactions directed towards the system memory;
determining, for each memory address mapping scheme:
a number of accesses for each memory bank, and
which bank of the plurality of banks has a highest number of memory accesses;
selecting one of the plurality of memory address mapping schemes for memory settings for the system memory based, at least in part, on:
the target addresses of the plurality of transactions, and
a determination of which memory address mapping scheme results in a lowest number of memory accesses among the banks determined to have the highest number of memory accesses.
2. The method of claim 1 , wherein the system memory comprises phase-change memory.
3. The method of claim 1 , wherein receiving a request to initialize the system memory is in response to a system reset.
4. The method of claim 1 , wherein the request to initialize a system memory is a system run-time request and method comprises:
flushing contents of the system memory.
5. An apparatus comprising:
a plurality of memory address mapping schemes; and
logic to
receive a request to initialize a system memory including a plurality of memory banks; and
during the initialization of the system memory:
execute, using the plurality of memory address mapping schemes, a system characterization workload including a plurality of transactions directed towards the system memory;
monitor target addresses of the plurality of transactions directed towards the system memory;
determine, for each memory address mapping scheme:
a number of accesses for each memory bank, and
which bank of the plurality of banks has a highest number of memory accesses;
select one of the plurality of memory address mapping schemes for memory settings for the system memory based, at least in part, on:
the target addresses of the plurality of transactions, and
a determination of which memory address mapping scheme results in a lowest number of memory accesses among the banks determined to have the highest number of memory accesses.
6. The apparatus of claim 5 , wherein the system memory comprises phase-change memory.
7. The apparatus of claim 5 , wherein receiving a request to initialize the system memory is in response to a system reset.
8. The apparatus of claim 5 , wherein the request to initialize a system memory is a system run-time request, and the logic to further:
flush contents of the system memory.
9. A system comprising:
a processor;
a memory;
a memory controller including a plurality of memory address mapping schemes; and
logic to
receive a request to initialize a system memory including a plurality of memory banks; and
during the initialization of the system memory:
execute, using the plurality of memory address mapping schemes, a system characterization workload including a plurality of transactions directed towards the system memory;
monitor target addresses of the plurality of transactions directed towards the system memory,
determine, for each memory address mapping scheme:
a number of accesses for each memory bank, and
which bank of the plurality of banks has a highest number of memory accesses;
select one of the plurality of memory address mapping schemes for memory settings for the system memory based, at least in part, on:
the target addresses of the plurality of transactions, and
a determination of which memory address mapping scheme results in a lowest number of memory accesses among the banks determined to have the highest number of memory accesses.
10. The system of claim 9 , wherein the memory comprises phase-change memory.
11. The system of claim 9 , wherein receiving a request to initialize the system memory is in response to a system reset.
12. The system of claim 9 , wherein the request to initialize a system memory is a system run-time request, and the logic to further:
flush contents of the system memory.