Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell
Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell are disclosed. An example apparatus includes a differential amplifier configured to amplify a voltage difference between voltages applied to first and second amplifier input nodes to provide an output. The example apparatus further includes first and second capacitances coupled to the first and second amplifier input nodes. A switch block coupled to the first and second capacitances is configured to couple during a first phase a reference input node to the first and second capacitances and to the first amplifier input node. The switch block is further configured to couple during the first phase an output of the amplifier to the second amplifier input node to establish a compensation condition. During a second phase, the switch block couples its input nodes to the first and second capacitances.
1. A method, comprising:
pre-charging a sense amplifier with a pre-charge voltage;
establishing a compensation voltage across inputs of a differential amplifier during a pre-charge phase of the sense amplifier, wherein establishing the compensation voltage across inputs of the differential amplifier comprises:
coupling a reference voltage to first and second nodes of a first capacitance coupled to the differential amplifier, a non-inverting input of the differential amplifier coupled to the second node of the first capacitance;
coupling the reference voltage to a first node of a second capacitance coupled to the differential amplifier, an inverting input of the differential amplifier coupled to a second node of the second capacitance; and
coupling an output of the differential amplifier to the second node of the second capacitance; and
evaluating a data state of a memory cell coupled to the sense amplifier.
2. The method of claim 1 , further comprising generating an output based on a voltage difference between inputs of the differential amplifier.
3. The method of claim 1 , wherein evaluating a data state of a memory cell coupled to the sense amplifier comprises:
coupling a data input to a first input of the differential amplifier; and
coupling a reference data input to a second input of the differential amplifier.
4. The method of claim 1 , wherein pre-charging a sense amplifier with a pre-charge voltage comprises enabling pre-charge transistors coupled to the sense amplifier and to a global bit line and a global reference bit line.
5. A method, comprising:
coupling a reference voltage to both sides of a first capacitance coupled to a first input of a differential amplifier during a pre-charge phase of a sense amplifier;
coupling the reference voltage to a first side of a second capacitance and coupling a second side of the second capacitance to an output of the differential amplifier during the pre-charge phase of the sense amplifier, wherein the second side of the second capacitance is coupled to a second input of the differential amplifier; and
performing memory cell evaluation by the sense amplifier.
6. The method of claim 5 , further comprising performing gain offset compensation for the sense amplifier during the pre-charge operation.
7. The method of claim 5 , further comprising performing voltage offset compensation for the sense amplifier during a pre-charge operation.
8. The method of claim 7 , wherein the first capacitance is coupled to a non-inverting input of the differential amplifier.
9. The method of claim 7 , wherein the second capacitance is coupled to an inverting input of the differential amplifier.
10. The method of claim 5 , wherein performing memory cell evaluation by the sense amplifier comprises coupling a memory cell to the sense amplifier during an evaluation operation.
11. The method of claim 10 , wherein performing memory cell evaluation by the sense amplifier comprises coupling a memory cell to the sense amplifier during an evaluation operation comprises coupling the sense amplifier to a global bit line and a global reference bit line, wherein the memory cell is coupled to the global bit line.
12. A method, comprising:
coupling both sides of a first capacitance to a reference voltage during a pre-charge phase of a sense amplifier, wherein the first capacitance is coupled to a first input of a differential amplifier;
coupling the reference voltage to a first node of a second capacitance;
coupling feedback from the differential amplifier to a second node of the second capacitance, wherein the second node of the second capacitance is further coupled to a second input of the differential amplifier; and
evaluating a voltage indicative of a data state of a memory cell coupled to the sense amplifier.
13. The method of claim 12 , further comprising establishing a compensation voltage across inputs of a differential amplifier during a pre-charge phase of the sense amplifier.
14. The method of claim 12 , wherein evaluating a voltage indicative of a data state of a memory cell coupled to the sense amplifier comprises coupling first and second inputs of the differential amplifier to a global bit line and a global reference bit line, respectively.
15. The method of claim 14 , wherein the first input of the differential amplifier is a non-inverting input and the second input of the differential amplifier is an inverting input.
16. The method of claim 12 , further comprising pre-charging the sense amplifier with a pre-charge voltage.
17. A method, comprising:
coupling a reference voltage to both sides of a first capacitance coupled to a first input of a differential amplifier during a pre-charge phase of a sense amplifier;
coupling the reference voltage to a first side of a second capacitance and coupling a second side of the second capacitance to an output of the differential amplifier during the pre-charge phase of the sense amplifier, wherein the second side of the second capacitance is coupled to a second input of the differential amplifier;
decoupling the reference voltage from the first capacitance during an evaluation phase of the sense amplifier;
decoupling the reference voltage and the output of differential amplifier from the second capacitance during the evaluation phase of the sense amplifier; and
coupling a global bit line and a global reference bit line to the inputs of the differential amplifier during the evaluation phase of the sense amplifier.