IP Library › Granted Patent US 9,406,572
Granted Patent B2
US 9,406,572 · App. 14/527,811 · Granted Aug 2, 2016

Method for processing a substrate and a method of process screening for integrated circuits

Inventors: Rudolf Zelsacher (Klagenfurt, AT); Peter Irsigler (Obernberg am Inn, AT); Erich Griebl (Dorfen, DE); Manfred Pirker (Klagenfurt, AT); Andreas Moser (Maria-Rain, AT)
Assignee: INFINEON TECHNOLOGIES AG
H01L22/14H01L21/02107H01L21/28158H01L21/768H01L29/66568
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Quick Facts
Patent No.
US 9,406,572
App. No.
14/527,811
Granted
Aug 2, 2016
Kind
B2
Abstract

According to various embodiments, a method for processing a substrate may include: forming a dielectric layer over the substrate, the dielectric layer may include a plurality of test regions; forming an electrically conductive layer over the dielectric layer to contact the dielectric layer in the plurality of test regions; simultaneously electrically examining the dielectric layer in the plurality of test regions, wherein portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions are electrically conductively connected with each other by an electrically conductive material; and separating the electrically conductive layer into portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions from each other.

Claims (64)

1. A method for processing a substrate, the method comprising:

forming a dielectric layer over the substrate, the dielectric layer comprising a plurality of test regions;

forming an electrically conductive layer over the dielectric layer to contact the dielectric layer in the plurality of test regions;

simultaneously electrically examining the dielectric layer in the plurality of test regions, wherein portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions are electrically conductively connected with each other by an electrically conductive material; and

separating the electrically conductive layer into portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions,

wherein simultaneously electrically examining comprises examining the dielectric strength of the dielectric layer in the plurality of test regions.

2. The method of claim 1 , further comprising:

forming a layer stack over the portions of the electrically conductive layer to provide a logical interconnection between the portions of the electrically conductive layer.

3. The method of claim 1 :

wherein the electrically conductive layer comprises a semiconducting material.

4. The method of claim 1 :

wherein separating the portions of the electrically conductive layer comprises forming a trench structure through at least the electrically conductive layer.

5. The method of claim 1 :

wherein the electrically conductive material is part of the electrically conductive layer.

6. The method of claim 5 :

wherein the portions of the electrically conductive layer are separated after the dielectric layer in the plurality of test regions having been examined.

7. The method of claim 1 , further comprising:

forming at least one source region and at least one drain region adjacent to one test region of the plurality of test regions to form a transistor structure.

8. The method of claim 1 ,

wherein forming the dielectric layer comprises forming a field dielectric structure separating the plurality of test regions from each other.

9. The method of claim 8 :

wherein a thickness of the dielectric layer in the plurality of test regions differs from a thickness of the dielectric layer in the field dielectric structure.

10. A method for processing a substrate, the method comprising:

forming a dielectric layer over the substrate, the dielectric layer comprising a plurality of test regions;

forming an electrically conductive layer over the dielectric layer to contact the dielectric layer in the plurality of test regions;

simultaneously electrically examining the dielectric layer in the plurality of test regions, wherein portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions are electrically conductively connected with each other by an electrically conductive material; and

separating the electrically conductive layer into portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions,

wherein the portions of the electrically conductive layer are separated before the dielectric layer in the plurality of test regions having been examined.

11. The method of claim 10 , further comprising:

forming a bridge structure electrically connecting the portions of the electrically conductive layer after having been separated, the bridge structure comprising the electrically conductive material.

12. The method of claim 11 :

wherein forming the bridge structure comprises disposing an electrically insulating mask between the electrically conductive material and the dielectric layer or disposing an electrically insulating mask between the electrically conductive material and the electrically conducting layer.

13. The method of claim 11 , further comprising:

wherein the electrically conductive material comprises a metal or a metal alloy.

14. The method of claim 11 , further comprising:

removing the bridge structure to uncover the portions of the electrically conductive layer for forming a layer stack over the portions of the electrically conductive layer.

15. A method comprising:

forming a field dielectric structure and a plurality of gate dielectric regions over an integrated circuit region of a substrate, the plurality of gate dielectric regions separated by the field dielectric structure;

electrically contacting the plurality of gate dielectric regions in parallel; and

simultaneously electrically examining the plurality of gate dielectric regions.

16. A method for processing a substrate, the method comprising:

forming a dielectric layer over the substrate, the dielectric layer comprising a plurality of test regions;

forming an electrically conductive layer over the dielectric layer to contact the dielectric layer in the plurality of test regions;

simultaneously electrically examining the dielectric layer in the plurality of test regions, wherein portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions are electrically conductively connected with each other by an electrically conductive material; and

separating the electrically conductive layer into portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions,

wherein simultaneously electrically examining comprises electrically coupling a test device to the portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions.

17. A method for processing a substrate, the method comprising:

forming a dielectric layer over the substrate, the dielectric layer comprising a plurality of test regions;

forming an electrically conductive layer over the dielectric layer to contact the dielectric layer in the plurality of test regions;

simultaneously electrically examining the dielectric layer in the plurality of test regions, wherein portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions are electrically conductively connected with each other by an electrically conductive material; and

separating the electrically conductive layer into portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions,

wherein simultaneously electrically examining comprises providing an electric field in the dielectric layer in the plurality of test regions.

18. A method for processing a substrate, the method comprising:

forming a dielectric layer over the substrate, the dielectric layer comprising a plurality of test regions;

forming an electrically conductive layer over the dielectric layer to contact the dielectric layer in the plurality of test regions;

simultaneously electrically examining the dielectric layer in the plurality of test regions, wherein portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions are electrically conductively connected with each other by an electrically conductive material;

separating the electrically conductive layer into portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions; and

at least partially removing the electrically conductive material to separate the portions of the electrically conductive layer from each other.

19. A method for processing a substrate, the method comprising:

forming a dielectric layer over the substrate, the dielectric layer comprising a plurality of test regions;

forming an electrically conductive layer over the dielectric layer to contact the dielectric layer in the plurality of test regions;

simultaneously electrically examining the dielectric layer in the plurality of test regions, wherein portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions are electrically conductively connected with each other by an electrically conductive material; and

separating the electrically conductive layer into portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions,

wherein forming an electrically conductive layer comprises forming a trench structure through at least the electrically conductive layer to electrically separate at least a first region of the electrically conductive layer from a second region of the electrically conductive layer, the first region of the electrically conductive layer comprising the portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 2, 2014
From: ZELSACHER, RUDOLF; IRSIGLER, PETER; GRIEBL, ERICH; PIRKER, MANFRED; MOSER, ANDREAS
To: INFINEON TECHNOLOGIES AG
Reel/Frame 034293/0017 →
Continuity (1)
Related Publication 20160126149A1 · May 5, 2016