Memory system and method of determining a failure in the memory system
An operating method of a memory system which includes a nonvolatile memory device including memory cells connected to a plurality of word lines, the operating method including pre-charging a selected one of the plurality of word lines; detecting a variation in a voltage or a current on the selected word line after the selected word line is floated; generating runtime failure information according to the detected variation; and determining a state of the selected word line or a state of a memory block including the selected word line, based on the runtime failure information.
1. An operating method of a memory system which includes a nonvolatile memory device including memory cells connected to a plurality of word lines, the operating method comprising:
pre-charging a selected one of the plurality of word lines;
detecting a variation in a voltage or a current on the selected word line after the selected word line is floated;
generating runtime failure information by converting the detected variation in the voltage or the current on the selected word line into a digital code; and
determining a state of the selected word line or a state of a memory block including the selected word line, based on the runtime failure information.
2. The operating method of claim 1 , wherein the selected word line or the memory block including the selected word line is determined to be in a normal state when a value of the runtime failure information is greater than a first reference value.
3. The operating method of claim 2 , wherein
the selected word line or the memory block including the selected word line is determined to be in a defective state when a value of the runtime failure information is smaller than a second reference value,
the second reference value is smaller than the first reference value, and
an access to the selected word line or the memory block including the selected word line is blocked when the selected word line or the memory block is determined to be in the defective state.
4. The operating method of claim 3 , wherein when a value of the runtime failure information is between the first reference value and the second reference value, the runtime failure information about the selected word line is detected whenever an erase operation is performed.
5. A memory system comprising:
a nonvolatile memory device configured to pre-charge a selected word line, detect a variation in a voltage or a current on the selected word line, and generate runtime failure information by converting the detected variation in the voltage or the current on the selected word line into a digital code; and
a controller configured to determine a state of the selected word line or a state of a memory block including the selected word line, based on the runtime failure information.
6. The memory system of claim 5 , wherein the nonvolatile memory device comprises:
a memory cell array including memory cells connected to word lines and bit lines;
an address decoder configured to provide a pre-charge voltage to a selected one of the word lines;
a voltage generator configured to generate the pre-charge voltage; and
control logic configured to generate the runtime failure information according to a result of detecting a variation in a voltage or a current on the selected word line after the selected word line is pre-charged with the pre-charge voltage.
7. The memory system of claim 6 , wherein the pre-charge voltage includes a program voltage or a read voltage.
8. The memory system of claim 6 , wherein the control logic comprises:
a sample/hold circuit configured to convert the detected variation in the voltage or the current of the selected word line into a step-shaped sample/hold voltage or current; and
an analog-to-digital converter configured to convert the sample/hold voltage or current into the digital code to generate the runtime failure information.
9. The memory system of claim 8 , wherein the control logic further comprises:
a comparing unit configured to compare the runtime failure information with a reference code to generate a word line pass signal or a word line fail signal; and
a pass/fail output unit configured to generate pass/fail information in response to the word line pass signal or the word line fail signal.
10. The memory system of claim 9 , wherein the controller is configured to block an access to the selected word line or the memory block including the selected word line according to the pass/fail information.
11. The memory system of claim 5 , wherein the controller is configured to set the selected word line or the memory block including the selected word line to a normal state when a value of the runtime failure information is greater than a first reference value.
12. The memory system of claim 11 , wherein the controller is configured to,
set the selected word line or the memory block including the selected word line to a defective state when a value of the runtime failure information is smaller than a second reference value, the second reference value being smaller than the first reference value, and
block an access to the selected word line or the memory block including the selected word line when the selected word line or the memory block is set to the defective state.
13. The memory system of claim 12 , wherein when a value of the runtime failure information is between the first reference value and the second reference value, the runtime failure information about the selected word line is detected whenever an erase operation is performed.
14. The memory system of claim 5 , wherein the nonvolatile memory device is configured to pre-charge the selected word line and detect the voltage or the current on the selected word line after a developing time elapses.
15. A nonvolatile memory device comprising:
a memory cell array including memory cells connected to word lines and bit lines;
an address decoder configured to provide a pre-charge voltage to a selected one of the word lines;
a voltage generator configured to generate the pre-charge voltage; and
a control logic configured to,
detect a variation in a voltage or a current on the selected word line after the selected word line is pre-charged with the pre-charge voltage, and
generate the runtime failure information by converting the detected variation in the voltage or the current on the selected word line into a digital code.
16. The nonvolatile memory device of claim 15 , wherein the control logic comprises:
a sample/hold circuit configured to convert the detected variation in the voltage or the current of the selected word line into a step-shaped sample/hold voltage or current; and
an analog-to-digital converter configured to convert the sample/hold voltage or current into the digital code to generate the runtime failure information.
17. The nonvolatile memory device of claim 16 , wherein the control logic further comprises:
a comparing unit configured to compare the runtime failure information with a reference code to generate a word line pass signal or a word line fail signal; and
a pass/fail output unit configured to generate pass/fail information in response to the word line pass signal or the word line fail signal.
18. The nonvolatile memory device of claim 15 , wherein the pre-charge voltage is a program voltage or a read voltage.