IP Library › Granted Patent US 9,412,858
Granted Patent B2
US 9,412,858 · App. 14/983,602 · Granted Aug 9, 2016

Group III nitride semiconductor device which can be used as a power transistor

Inventors: Hideyuki Okita (Toyama, JP); Masahiro Hikita (Toyama, JP); Yasuhiro Uemoto (Toyama, JP)
Assignee: PANASONIC INTELLECTUAL PEOPERTY MANAGEEMENT CO., LTD.
H01L29/7789H01L29/2003H01L29/205H01L29/7787H01L29/7788
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Quick Facts
Patent No.
US 9,412,858
App. No.
14/983,602
Granted
Aug 9, 2016
Kind
B2
Abstract

A semiconductor device includes a substrate, a first nitride semiconductor layer formed on the substrate, a p-type nitride semiconductor layer formed on the first nitride semiconductor layer, a recess having a bottom portion which reaches the first nitride semiconductor layer through a part of the p-type nitride semiconductor layer, a third nitride semiconductor layer formed to cover the bottom portion of the recess, a side portion of the recess, and a part of an upper surface of the p-type nitride semiconductor layer. The semiconductor device further includes a fourth nitride semiconductor layer formed on the third nitride semiconductor layer, a first electrode formed on another side of the substrate, a gate electrode formed on the upper surface of the p-type nitride semiconductor layer, and a second electrode that is in contact with the third nitride semiconductor layer or the fourth nitride semiconductor layer. The third nitride semiconductor layer has a bandgap different from a bandgap of the fourth nitride semiconductor layer.

Claims (22)

1. A semiconductor device comprising:

a substrate;

a first nitride semiconductor layer formed on the substrate;

a p-type nitride semiconductor layer formed on the first nitride semiconductor layer;

a recess having a bottom portion which reaches the first nitride semiconductor layer through a part of the p-type nitride semiconductor layer;

a third nitride semiconductor layer formed to cover the bottom portion of the recess, a side portion of the recess, and a part of an upper surface of the p-type nitride semiconductor layer;

a fourth nitride semiconductor layer formed on an upper surface of the third nitride semiconductor layer;

a first electrode formed on a rear surface of the substrate;

a gate electrode formed on the upper surface of the p-type nitride semiconductor layer; and

a second electrode that is in contact with the third nitride semiconductor layer or the fourth nitride semiconductor layer, wherein

the third nitride semiconductor layer has a bandgap different from a bandgap of the fourth nitride semiconductor layer.

2. The semiconductor device according to claim 1 , wherein the fourth nitride semiconductor layer has the bandgap greater than the bandgap of the third nitride semiconductor layer.

3. The semiconductor device according to claim 2 , wherein a thickness of the fourth nitride semiconductor layer is greater in a portion of the fourth nitride semiconductor layer formed along the bottom portion of the recess and the upper surface of the p-type nitride semiconductor layer than in a portion of the fourth nitride semiconductor layer formed along the side portion of the recess.

4. The semiconductor device according to claim 2 , wherein a thickness of the third nitride semiconductor layer is greater in a portion of the third nitride semiconductor layer formed along the bottom portion of the recess and the upper surface of the p-type nitride semiconductor layer than in a portion of the third nitride semiconductor layer formed along the side portion of the recess.

5. The semiconductor device according to claim 2 , wherein the side portion of the recess has a tapered angle that falls within a range from 40 degrees to 80 degrees both inclusive.

6. The semiconductor device according to claim 2 , further comprising a fifth nitride semiconductor layer between the first nitride semiconductor layer and the p-type nitride semiconductor layer,

wherein a bottom portion of the fifth nitride semiconductor layer is located above the bottom portion of the recess.

7. The semiconductor device according to claim 1 , wherein the third nitride semiconductor layer has the bandgap greater than the bandgap of the fourth nitride semiconductor layer.

8. The semiconductor device according to claim 7 , wherein a thickness of the third nitride semiconductor layer is greater in a portion of the third nitride semiconductor layer formed along the bottom portion of the recess and the upper surface of the p-type nitride semiconductor layer than in a portion of the third nitride semiconductor layer formed along the side portion of the recess.

9. The semiconductor device according to claim 7 , wherein the side portion of the recess has a tapered angle that is between 40 degrees and 80 degrees both inclusive.

10. The semiconductor device according to claim 7 , further comprising a fifth nitride semiconductor layer between the first nitride semiconductor layer and the p-type nitride semiconductor layer,

wherein a bottom portion of the fifth nitride semiconductor layer is located above the bottom portion of the recess.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 17, 2016
From: OKITA, HIDEYUKI; HIKITA, MASAHIRO; UEMOTO, YASUHIRO
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 037505/0870 →
Priority Claims (1)
JP 2013-146125 · Jul 12, 2013 · national
Continuity (2)
Continuation PCTJP2014003233 · Jun 17, 2014
Related Publication 20160118491A1 · Apr 28, 2016