Circuits and methods for photovoltaic inverters
View Patent ↗Circuits and methods for photovoltaic inverters are provided. In some embodiments, a power inverter circuit is provided, the inverter comprising: an input terminal for a direct current source coupled to a first conductor; a first side of a capacitor coupled to the input terminal; a second input terminal for the direct current source coupled to first sides of a first switch and second switch; a second side of the capacitor coupled to first sides of a third switch and fourth switch; a first side of a first inductor coupled to the first input terminal, the first side of the capacitor and the first conductor; a second side of the first inductor coupled to second sides of the first switch and third switch; and a first side of a second inductor coupled to a second conductor, and second sides of the second switch and fourth switch.
1. A power inverter circuit comprising:
a first input terminal for connection to a first side of a direct current source coupled to a first conductor of an alternating current transmission line;
a first side of a capacitor coupled to the first input terminal;
a second input terminal for connection to a second side of the direct current source coupled to a first side of a first switch and a first side of a second switch;
a second side of the capacitor coupled to a first side of a third switch and a first side of a fourth switch;
a first side of a first inductor coupled to the first input terminal, the first side of the capacitor and the first conductor;
a second side of the first inductor coupled to a second side of the first switch and a second side of the third switch; and
a first side of a second inductor coupled to a second conductor of an alternating current transmission line, a second side of the second switch and a second side of the fourth switch.
2. The power inverter circuit of claim 1 , wherein the capacitor has a capacitance that allows a voltage across the capacitor to vary over a range of between 100 percent and 200 percent of a voltage across the first conductor and the second conductor during operation of the power inverter circuit.
3. The power inverter circuit of claim 1 , wherein the second input terminal is coupled to a first side of a fifth switch, and wherein the power inverter circuit further comprises:
a sixth switch with a first side coupled to a first side of the second side of the third switch and a first side of the fourth switch, and a second side of the sixth switch coupled to a second side of the fifth switch and a first side of a third inductor, wherein a second side of the third inductor is coupled to a third conductor of the alternating current transmission line.
4. The power inverter circuit of claim 3 , further comprising a control circuit that controls a phase shift between first control signals that control a state of the second switch and a state of the fourth switch and second control signals that control a state of the fifth switch and a state of the sixth switch to reduce a switching frequency ripple in a current on the first conductor.
5. The power inverter circuit of claim 1 , further comprising:
a control circuit that controls a state of the first switch and that controls a state of the third switch such that a maximum power point of an output of a direct current source coupled across the first input terminal and the second input is tracked, the control circuit comprising:
a maximum power point tracking circuit that uses a voltage output of the direct current source and a current output of the direct current source as inputs, and that outputs a reference current for the direct current source; and
a proportional integral controller that uses a difference between the reference current and the current output of the direct source as an input, and that outputs a duty cycle at which to control the first switch and the third switch to yield a maximum power output from the direct current source.
6. The power inverter circuit of claim 1 , further comprising:
a control circuit that controls a state of the second switch and that controls a state of the fourth switch such that power conversion efficiency of the power inverter circuit is maximized based on a voltage output of the direct current source, a current output of the direct current source, and a voltage of the second conductor of the alternating current transmission line.
7. The power inverter circuit of claim 6 , wherein the state of the second switch and the state of the fourth switch is controlled based on an output of either (i) a pulse width modulator, or (ii) a hysteresis controller.
8. The power inverter circuit of claim 1 , further comprising a control circuit that controls a phase shift between first control signals that control a state of the first switch and a state of the third switch and second control signals that control a state of the third switch and a state of the fourth switch to reduce a switching frequency ripple in a voltage across the first conductor and the second conductor.
9. The power inverter circuit of claim 1 , further comprising a photovoltaic direct current source coupled between the first input terminal and the second input terminal.
10. The power inverter circuit of claim 1 , wherein an output voltage of the power inverter circuit is an alternating current signal having a root mean square voltage of between 120 V RMS and 240 V RMS.
11. The power inverter of claim 1 , wherein the capacitor has a capacitance of between about 10 microfarads per kilowatt of output power and about 30 microfarads per kilowatt of power.
12. A power inverter circuit comprising:
a first input terminal means for connecting to a first side of a direct current source and coupled to a first conductor of an alternating current transmission line;
a first side of a capacitance means for causing a capacitance to be provided coupled to the first input terminal means;
a second input terminal means for connecting to a second side of the direct current source and coupled to a first side of a first switching means for causing a first circuit to be alternately substantially shorted or opened and coupled to a first side of a second switching means for causing a second circuit to be alternately substantially shorted or opened;
a second side of the capacitor means coupled to a first side of a third switching means for causing a third circuit to be alternately substantially shorted or opened and a first side of a fourth switching means for causing a fourth circuit to be alternately substantially shorted or opened;
a first side of a first induction means for causing an inductance to be provided coupled to the first input terminal means, the first side of the capacitance means and the first conductor;
a second side of the first induction means coupled to a second side of the first switching means and a second side of the third switching means; and
a first side of a second induction means for causing an inductance to be provided coupled to a second conductor of an alternating current transmission line, a second side of the second switching means and a second side of the fourth switching means.
13. The power inverter circuit of claim 12 , wherein the capacitance means provides a capacitance that allows a voltage across the capacitance means to vary over a range of between 100 percent and 200 percent of a voltage across the first conductor and second conductor during operation of the power inverter circuit.
14. The power inverter circuit of claim 12 , wherein the second input terminal means is coupled to a first side of a fifth switching means for causing a fifth circuit to be alternately substantially shorted or opened, and wherein the power inverter circuit further comprises:
a sixth switching means for causing a sixth circuit to be alternately substantially shorted or opened having a first side coupled to a first side of the second side of the third switching means and a first side of the fourth switching means, and a second side of the sixth switching means coupled to a second side of the fifth switching means and a first side of a third induction means for causing an inductance to be provided, wherein a second side of the third induction means is coupled to a third conductor of the alternating current transmission line.
15. The power inverter circuit of claim 14 , further comprising control means for controlling a phase shift between first control signals that control a state of the second switch and a state of the fourth switch and second control signals that control a state of the fifth switch and a state of the sixth switch to reduce a switching frequency ripple in a current on the first conductor.
16. The power inverter circuit of claim 12 , further comprising:
a control means for controlling a state of the first switch and a state of the third switch such that a maximum power point of an output of a direct current source coupled across the first input terminal and the second input is tracked, the control circuit comprising:
a maximum power point tracking means for outputting a reference current for the direct current source using a voltage output of the direct current source and a current output of the direct current source as inputs; and
a proportional integral controlling means for outputting a duty cycle at which to control the first switch and the third switch to yield a maximum power output from the direct current source that uses a difference between the reference current and the current output of the direct source as an input.
17. The power inverter circuit of claim 12 , further comprising:
a control means for controlling a state of the second switching means and a state of the fourth switching means for maximizing a power conversion efficiency of the power inverter circuit is based on a voltage output of the direct current source, a current output of the direct current source, and a voltage of the second conductor of the alternating current transmission line.
18. The power inverter circuit of claim 17 , wherein the state of the second switch and the state of the fourth switching means is controlled based on an output of either (i) a pulse width modulating means for driving the second switching means and the fourth switching means, or (ii) a hysteresis controlling means for driving the second switching means and the fourth switching means.
19. The power inverter circuit of claim 12 , further comprising a control means for controlling a phase shift between first control signals that control a state of the first switch and a state of the third switch and second control signals that control a state of the third switch and a state of the fourth switch to reduce a switching frequency ripple in a voltage across the first conductor and the second conductor.
20. The power inverter circuit of claim 12 , further comprising a photovoltaic direct current means for supplying a direct current coupled between the first input terminal means and the second input terminal means.
21. The power inverter circuit of claim 12 , wherein an output voltage of the power inverter circuit is an alternating current signal having a root mean square voltage of between 120 V RMS and 240 V RMS.
22. The power inverter of claim 12 , wherein the capacitance means provides a capacitance of between about 10 microfarads per kilowatt of output power and about 30 microfarads per kilowatt of power.