Semiconductor device and method for fabricating the same

1. A semiconductor device comprising:

a semiconductor substrate including a first region and a second region;

an interlayer insulating layer formed on the semiconductor substrate;

a semiconductor element formed on the semiconductor substrate in the first region, the semiconductor element including a gate structure formed in the interlayer insulating layer;

an isolation layer formed in the semiconductor substrate in the second region;

a through-silicon via formed to penetrate the semiconductor substrate, the interlayer insulating layer, and the isolation layer in the second region;

a first conduction type first impurity region contacting with the isolation layer and the through-silicon via and formed to surround only a portion of a sidewall of the through-silicon via in the semiconductor substrate in the second region; and

a first conduction type second impurity region arranged to overlap the gate structure in the semiconductor substrate in the first region,

wherein the first impurity region and the second impurity region are separated from each other.

2. The semiconductor device of claim 1 , wherein a depth of first impurity region is shallower than a depth of the through-silicon via.

3. The semiconductor device of claim 1 , wherein the first conduction type is an n-type.

4. The semiconductor device of claim 1 , wherein a doping concentration of the first impurity region is 1E14 ions/cm3 to 1E16 ions/cm3.

5. The semiconductor device of claim 1 , wherein the first and second impurity regions intercept diffusion of a second conduction type charges into the semiconductor element.

6. The semiconductor device of claim 1 , wherein the first impurity region is below the isolation layer.

7. The semiconductor device of claim 1 , wherein the gate structure includes a gate insulating layer on the semiconductor substrate, a gate electrode on the gate insulating layer, and a spacer on a side wall of the gate electrode.

8. The semiconductor device of claim 7 , further comprising a first conduction type second impurity region surrounding only a portion of a sidewall of the through-silicon via in the semiconductor substrate.

9. A semiconductor device comprising:

a semiconductor substrate comprising a first region and a second region;

an interlayer insulating layer on the semiconductor substrate;

a semiconductor element on the semiconductor substrate in the first region of the semiconductor substrate, the semiconductor element including a gate structure in the interlayer insulating layer;

a first isolation layer in the semiconductor substrate in the first region of the semiconductor substrate;

a via hole in the second region of the semiconductor substrate, the via hole penetrating the semiconductor substrate and the interlayer insulating layer;

a through-silicon via in the via hole; and

a first conduction type first impurity region contacting the first isolation layer and arranged to overlap the gate structure in the semiconductor substrate to intercept diffusion of a second conduction type charges into the semiconductor element.

10. A semiconductor device comprising:

a semiconductor substrate including a first region and a second region;

an interlayer insulating layer on the semiconductor substrate;

a semiconductor element on the semiconductor substrate in the first region, the semiconductor element including a gate structure;

a first isolation layer in the semiconductor substrate, the first isolation layer defining the first region;

a second isolation layer in the semiconductor substrate in the second region;

a through-silicon via penetrating the semiconductor substrate, the interlayer insulating layer, and the isolation layer in the second region;

a first conduction type first impurity region contacting with the through-silicon via and surrounding only a portion of a sidewall of the through-silicon via in the semiconductor substrate in the second region; and

a first conduction type second impurity region contacting the first isolation layer and arranged to overlap the gate structure in the semiconductor substrate in the first region.

11. The semiconductor device claim 10 , wherein a depth of first impurity region is shallower than a depth of the through-silicon via.

12. The semiconductor device of claim 10 , wherein the first conduction type is an n-type.

13. The semiconductor device claim 10 , wherein the first conduction type first impurity region is formed to come in contact with the second isolation layer.