Semiconductor device
A semiconductor device including a semiconductor chip, a first electrode pad and second electrode pad included on one surface of the semiconductor chip, a first conductive post joined by a joining material to the first electrode pad, a plurality of second conductive posts joined by a joining material to the second electrode pad, and a printed substrate, disposed opposing the one surface of the semiconductor chip, on which is formed an electrical circuit to which the first conductive post and second conductive posts are connected. The second conductive posts on the side near the first conductive post are arrayed avoiding a short-circuit prevention region at a distance such that the joining material of the first conductive post and the joining material of the second conductive posts do not link.
1. A semiconductor device, comprising:
a semiconductor chip;
a first electrode pad and second electrode pad included on the semiconductor chip;
a first conductive post connected to the first electrode pad by a joining material;
a plurality of second conductive posts connected to the second electrode pad by a joining material; and
a printed substrate including an electrical circuit to which the first conductive post and second conductive posts are connected, wherein
the first electrode pad is disposed opposing an intermediate portion of an edge of the second electrode pad, and
the plurality of second conductive posts are arrayed outside a short-circuit prevention region positioned between two of the second conductive posts arrayed on a side of the second electrode pad near the first conductive post, the short-circuit prevention region including a point of intersection of a first imaginary line bisecting the two of the second conductive posts and a second imaginary line, the second imaginary line being perpendicular to the first imagery line and bisecting the first conductive post, and the short-circuit prevention region being free of any second conductive posts.
2. The semiconductor device according to claim 1 , wherein
the two second conductive posts are arrayed in positions at either end side of the edge of the second electrode pad.
3. The semiconductor device according to claim 1 , wherein
the plurality of second conductive posts are arrayed in an arc form.
4. The semiconductor device according to claim 3 , wherein an interval between the two second conductive posts is greater than the interval between other second conductive posts of the plurality of second conductive posts.
5. The semiconductor device according to claim 1 , further comprising an isolation layer disposed on the short-circuit prevention region.
6. The semiconductor device according to claim 2 , further comprising an isolation layer disposed on the short-circuit prevention region.
7. The semiconductor device according to claim 3 , further comprising an isolation layer disposed on the short-circuit prevention region.
8. The semiconductor device according to claim 4 , further comprising an isolation layer disposed on the short-circuit prevention region.
9. The semiconductor device according to claim 1 , wherein the second electrode pad is divided into a plurality of sub-regions in a direction away from the first electrode pad, and the plurality of sub-regions are connected by wiring.
10. The semiconductor device according to claim 2 , wherein the second electrode pad is divided into a plurality of sub-regions in a direction away from the first electrode pad, and the plurality of sub-regions are connected by wiring.
11. The semiconductor device according to claim 1 , wherein the second electrode pad is divided into a plurality of sub-regions perpendicular to a direction away from the first electrode pad, and the plurality of sub-regions are connected by wiring.
12. The semiconductor device according to claim 2 , wherein the second electrode pad is divided into a plurality of sub-regions perpendicular to a direction away from the first electrode pad, and the plurality of sub-regions are connected by wiring.
13. The semiconductor device according to claim 1 , further comprising an isolation layer disposed on the short-circuit prevention region, wherein an interval between the two second conductive posts is greater than the interval between other second conductive posts of the plurality of second conductive posts.
14. A semiconductor device, comprising:
a semiconductor chip;
a first electrode pad and second electrode pad included on the semiconductor chip, the second electrode pad being divided into a plurality of sub-regions in a direction away from the first electrode pad, the plurality of sub-regions including a first sub-region, a second sub-region, and a third sub-region;
a first conductive post connected to the first electrode pad by a joining material;
a plurality of second conductive posts connected to the second electrode pad by a joining material; and
a printed substrate including an electrical circuit to which the first conductive post and second conductive posts are connected, wherein
the first electrode pad is disposed opposing an intermediate portion of an edge of the first sub-region of the second electrode pad,
the second sub-region of the second electrode pad includes second conductive posts respectively disposed at sides and a central portion of the second sub-region,
the third sub-region of the second electrode pad includes second conductive posts respectively disposed at the sides and the central portion of the third sub-region, and
the first sub-region of the second electrode pad includes second conductive posts respectively disposed at the sides of the first sub-region, the central portion of the first sub-region being free from any second conductive posts.
15. The semiconductor device according to claim 14 , wherein
the second sub-region of the second electrode pad includes first and second conductive posts respectively disposed at first and second sides of the second sub-region and a third second conductive post disposed in the central portion of the second sub-region,
the third sub-region of the second electrode pad includes fourth and fifth second conductive posts respectively disposed at third and fourth sides of the third sub-region and a sixth second conductive post disposed in the central portion of the third sub-region, and
the first sub-region of the second electrode pad includes seventh and eighth second conductive posts respectively disposed at fifth and sixth sides of the first sub-region, the seventh and eighth second conductive posts being the only second conductive posts disposed in the first sub-region.