Junctionless tunnel FET with metal-insulator transition material
Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a doped semiconductor layer having a substantially uniform doping profile; a first gate structure positioned on the doped semiconductor layer; and a second gate structure positioned on the doped semiconductor layer, the second gate structure including a metal-insulator transition material and a gate dielectric layer separating the metal-insulator transition material from the doped semiconductor layer.
1. A method of forming an integrated circuit (IC) structure, the method comprising:
forming a doped semiconductor layer on an insulator layer, the doped semiconductor layer having a substantially uniform doping profile;
forming a dielectric layer on the doped semiconductor layer;
forming a first gate material and a second gate material on the dielectric layer, wherein the second gate material includes a metal-insulator transition material; and
forming a source contact at an end of the doped semiconductor layer and forming a drain contact at an opposing end of the doped semiconductor layer, wherein a separation distance between the first gate material and the second gate material is larger than a separation distance between the second gate material and the source contact.
2. The method of claim 1 , wherein the metal-insulator transition material comprises vanadium oxide.
3. The method of claim 1 , wherein the forming of the doped semiconductor layer further includes doping a semiconductor layer with one of a p-type dopant and an n-type dopant to create the substantially uniform doping profile.
4. The method of claim 1 , wherein the substantially uniform doping profile of the doped semiconductor layer is between approximately 1.0 ×10 19 atoms per cubic centimeter (atoms/cm 3 ) and approximately 3.0 ×10 19 atoms/cm 3 .
5. The method of claim 1 , further comprising electrically biasing the first gate material to create a difference in electric potential between the second gate material and the doped semiconductor layer and increase a conductivity of the second gate material.
6. The method of claim 1 , further comprising forming an interlayer contact on each of the first gate material and the second gate material.
7. The method of claim 1 , wherein the dielectric layer comprises hafnium oxide (HfO 2 ).
8. A method of forming an integrated circuit (IC) structure, the method comprising:
forming a doped semiconductor layer on an insulator layer, the doped semiconductor layer having a substantially uniform doping profile;
forming a dielectric layer on the doped semiconductor layer;
forming a first gate material and a second gate material on the dielectric layer, wherein the second gate material includes a metal-insulator transition material; and
electrically biasing the first gate material to create a difference in electric potential between the second gate material and the doped semiconductor layer and increase a conductivity of the second gate material.
9. The method of claim 8 , wherein the metal-insulator transition material comprises vanadium oxide.
10. The method of claim 8 , wherein the forming of the doped semiconductor layer further includes doping a semiconductor layer with one of a p-type dopant and an n-type dopant to create the substantially uniform doping profile.
11. The method of claim 8 , further comprising forming a source contact at an end of the doped semiconductor layer and forming a drain contact at an opposing end of the doped semiconductor layer.
12. The method of claim 11 , wherein a separation distance between the first gate material and the second gate material is larger than a separation distance between the second gate material and the source contact.
13. The method of claim 8 , wherein the substantially uniform doping profile of the doped semiconductor layer is between approximately 1.0 ×10 19 atoms per cubic centimeter (atoms/cm3) and approximately 3.0 ×10 19 atoms/cm 3 .
14. The method of claim 8 , further comprising electrically biasing the first gate material to create a difference in electric potential between the second gate material and the doped semiconductor layer and increase a conductivity of the second gate material.
15. The method of claim 8 , further comprising forming an interlayer contact on each of the first gate material and the second gate material.
16. The method of claim 8 , wherein the dielectric layer comprises hafnium oxide (HfO 2 ).
17. A method of forming an integrated circuit (IC) structure, the method comprising:
providing a structure including:
a doped semiconductor layer positioned on an insulator layer, the doped semiconductor layer having a substantially uniform doping profile,
a dielectric layer positioned on the doped semiconductor layer,
a first gate material positioned on the dielectric layer, and
a second gate material on the dielectric layer, wherein the second gate material includes a metal-insulator transition material; and
electrically biasing the first gate material to create a difference in electric potential between the second gate material and the doped semiconductor layer and increase a conductivity of the second gate material.
18. The method of claim 17 , wherein the dielectric layer comprises hafnium oxide (HfO 2 ).
19. The method of claim 17 , further comprising forming a source contact at an end of the doped semiconductor layer and forming a drain contact at an opposing end of the doped semiconductor layer.
20. The method of claim 19 , wherein a separation distance between the first gate material and the second gate material is larger than a separation distance between the second gate material and the source contact.