Wafer bonding process and structure
A semiconductor device and a method of fabricating the same are introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and one or more conductive pads are formed in the recesses. One or more barrier layers are formed between the passivation layers and the conductive pads. The conductive pads of the first substrate are aligned to the conductive pads of a second substrate and are bonded using a direct bonding method.
1. A method comprising:
forming a first passivation layer over a first substrate;
forming a first recess in the first passivation layer;
forming a first barrier layer in the first recess;
forming a first conductive pad in the first recess of the first passivation layer such that the first barrier layer is interposed between the first conductive pad and the first passivation layer; and
bonding a second conductive pad on a second substrate directly to the first conductive pad.
2. The method of claim 1 , wherein forming the first barrier layer further comprises forming a first barrier sublayer and a second barrier sublayer in the first recess of the first passivation layer, wherein a reduction potential difference between the first barrier layer and the first conductive pad is between about −1V and about +1V.
3. The method of claim 1 , further comprising:
forming a second passivation layer over the second substrate;
forming a second recess in the second passivation layer;
forming a second barrier layer in the second recess; and
forming the second conductive pad in the second recess of the second passivation layer such that the second barrier layer is interposed between the second conductive pad and the second passivation layer.
4. The method of claim 3 , further comprising bonding the first passivation layer to the second passivation layer using a direct dielectric-to-dielectric bonding method.
5. The method of claim 4 , further comprising bonding the first conductive pad to the second conductive pad using a direct metal-to-metal bonding method.
6. The method of claim 5 , further comprising annealing at a temperature between about 250 C and about 400 C for a time period between about 0.5 hr and about 4 hrs.
7. A method comprising:
forming a first passivation layer over a first substrate;
forming a first plurality of recesses in the first passivation layer;
forming a first barrier layer in the first plurality of recess; and
forming a first plurality of conductive pads in the first plurality of recesses, the first barrier layer contacting bottoms and sidewalls of the first plurality of conductive pads, wherein a reduction potential difference between the first barrier layer and each of the first plurality of conductive pads is between about −1V and about +1V.
8. The method of claim 7 , wherein forming the first barrier layer comprises:
forming a first barrier sublayer in the first plurality of recess; and
forming a second barrier sublayer over the first barrier sublayer.
9. The method of claim 8 , wherein the first barrier sublayer comprises tantalum nitride (TaN) and the second barrier sublayer comprises cobalt (Co), nickel (Ni), or iron (Fe).
10. The method of claim 7 , wherein forming the first passivation layer comprises:
forming a first passivation sublayer over the first substrate;
forming a second passivation sublayer over the first passivation sublayer;
forming a third passivation sublayer over the second passivation sublayer; and
forming a fourth passivation sublayer over the third passivation sublayer.
11. The method of claim 10 , wherein the first passivation sublayer comprises undoped silicon glass (USG), the second passivation sublayer comprises silicon nitrade (SiN), the third passivation sublayer comprises USG, and the fourth passivation sublayer comprises silicon oxynitrade (SiON).
12. The method of claim 10 , wherein the first plurality of recesses extends through the fourth passivation sublayer, the third passivation sublayer, and the second passivation sublayer.
13. The method of claim 7 , further comprising planarizing the first plurality of conductive pads such that topmost surfaces of the first plurality of conductive pads are coplanar with a topmost surface of the first passivation layer.
14. A method comprising:
forming a first structure, wherein forming the first structure comprises:
forming a first passivation layer over a first substrate;
patterning the first passivation layer to form a first plurality of recesses in the first passivation layer;
forming a first barrier layer on bottoms and sidewalls of the first plurality of recesses, the first barrier layer comprising a first barrier sublayer formed of a first material and a second barrier sublayer formed of a second material, the first material being different from the second material; and
filling the first plurality of recesses with a third material to form a first plurality of conductive pads, the third material being different from the first material and the second material; and
directly bonding the first structure to a second structure, the second structure comprising a second substrate having a second plurality of conductive pads thereon, wherein the second structure is bonded to the first structure such that the first plurality of conductive pads are aligned with and bonded to respective ones of the second plurality of conductive pads.
15. The method of claim 14 , further comprising:
forming a second passivation layer over the second substrate;
patterning the second passivation layer to form a second plurality of recesses in the second passivation layer;
forming a second barrier layer over the second passivation layer, the second barrier layer comprising a third barrier sublayer and a fourth barrier sublayer; and
forming the second plurality of conductive pads over the second barrier layer in the second plurality of recesses.
16. The method of claim 15 , wherein a reduction potential difference between the second barrier layer and each of the second plurality of conductive pads is between about −1V and about +1V.
17. The method of claim 14 , wherein a reduction potential difference between the first barrier layer and each of the first plurality of conductive pads is between about −1V and about +1V.
18. The method of claim 14 , further comprising removing excess portions of the third material such that topmost surfaces the first plurality of conductive pads are coplanar with a topmost surface of the first passivation layer.
19. The method of claim 14 , wherein directly bonding the first structure to the second structure comprises:
directly bonding the first passivation layer to a second passivation layer disposed over the second substrate; and
directly bonding the first plurality of conductive pads to respective ones of the second plurality of conductive pads.
20. The method of claim 14 , wherein forming the first passivation layer comprises:
forming a first passivation sublayer comprising undoped silicon glass (USG) over the first substrate;
forming a second passivation sublayer comprising silicon nitrade (SiN) over the first passivation sublayer;
forming a third passivation sublayer comprising USG over the second passivation sublayer; and
forming a fourth passivation sublayer comprising silicon oxynitrade (SiON) over the third passivation sublayer.