Transistor with wurtzite channel
A device includes a source region, a drain region, and a wurtzite semiconductor between the source region and the drain region. A source-drain direction is parallel to a [01-10] direction or a [−2110] direction of the wurtzite semiconductor. The device further includes a gate dielectric over the wurtzite semiconductor, and a gate electrode over the gate dielectric.
1. A device comprising:
a source region;
a drain region;
a wurtzite semiconductor between the source region and the drain region, wherein a source-drain direction is parallel to a [01-10] direction or a [−2110] direction of the wurtzite semiconductor;
a gate dielectric over the wurtzite semiconductor; and
a gate electrode over the gate dielectric.
2. The device of claim 1 , wherein the source-drain direction is parallel to the [01-10] direction of the wurtzite semiconductor.
3. The device of claim 2 , wherein the wurtzite semiconductor comprises direct-band wurtzite silicon or direct-band wurtzite germanium.
4. The device of claim 1 , wherein the source-drain direction is parallel to the [−2110] direction of the wurtzite semiconductor.
5. The device of claim 4 , wherein the wurtzite semiconductor comprises indirect-band wurtzite silicon.
6. The device of claim 1 further comprising a substrate, with the wurtzite semiconductor over and contacting the substrate, wherein the substrate is formed of a material having a hexagonal structure.
7. The device of claim 6 , wherein the substrate comprises silicon oxide, gallium nitride, gallium phosphorous, or diamond cubic silicon.
8. The device of claim 1 , wherein the source region, the drain region, the wurtzite semiconductor, the gate dielectric, and the gate electrode form a Fin Field-Effect Transistor (FinFET).
9. The device of claim 1 , wherein the source region, the drain region, the wurtzite semiconductor, the gate dielectric, and the gate electrode form a double-gate planar transistor.
10. The device of claim 1 , wherein the source region, the drain region, the wurtzite semiconductor, the gate dielectric, and the gate electrode form a vertical gate-all-around transistor.
11. A device comprising:
a substrate;
a channel region over the substrate, with the channel region formed of a wurtzite semiconductor comprising silicon or germanium;
a source region;
a drain region, wherein a source-drain direction interconnecting the source region and the drain region is parallel to a [01-10] direction or a [−2110] direction of the wurtzite semiconductor;
a gate dielectric comprising a portion overlapping the channel region; and
a gate electrode over the gate dielectric.
12. The device of claim 11 , wherein the wurtzite semiconductor comprises direct-band wurtzite silicon or direct-band wurtzite germanium.
13. The device of claim 12 , wherein the source-drain direction is parallel to the [01-10] direction, and a [0001] direction of the wurtzite semiconductor is parallel to a major surface of the substrate.
14. The device of claim 11 , wherein the wurtzite semiconductor comprises indirect-band wurtzite silicon.
15. The device of claim 14 , wherein the source-drain direction is parallel to the [−2110] direction of the wurtzite semiconductor, and a [01-10] direction of the channel region is parallel to a major surface of the substrate.
16. A device comprising:
a substrate;
dielectric regions over the substrate;
a wurtzite semiconductor strip over the substrate and between opposite portions of the dielectric regions, wherein a top portion of the wurtzite semiconductor strip protrudes over top surfaces of the dielectric regions to form a wurtzite semiconductor fin, and a lengthwise direction of the wurtzite semiconductor strip is parallel to a [01-10] direction or a [−2110] direction of the wurtzite semiconductor strip;
a gate dielectric over a top surface and on sidewalls of the wurtzite semiconductor fin; and
a gate electrode over the gate dielectric.
17. The device of claim 16 further comprising:
a source region and a drain region on opposite sides of the gate electrode, wherein the lengthwise direction of the wurtzite semiconductor strip is parallel to a source-to-drain direction or a drain-to-source direction of a transistor comprising the wurtzite semiconductor fin.
18. The device of claim 16 , wherein a bottom surface of the wurtzite semiconductor strip contacts a top surface of the substrate, and wherein the substrate comprises a hexagonal structure.
19. The device of claim 16 further comprising a wurtzite semiconductor region overlapping the substrate and overlapped by one of the dielectric regions.
20. The device of claim 16 , wherein a bottom surface of the dielectric regions is in contact with a top surface of the substrate.