Sampling clock adjustment for an analog to digital converter of a receiver

1. A receiver comprising:

an analog to digital converter to convert an analog input signal into at least one digital input signal at timings controlled by a sampling clock;

a finite impulse response filter to generate at least one filtered input signal based on the at least one digital input signal;

a data decision circuit to generate recovered data based on the at least one filtered input signal; and

a feedback loop coupled to receive the at least one filtered input signal and to receive the recovered data and to generate the sampling clock based on the at least one filtered input signal and the recovered data, the feedback look comprising:

a signal reconstruction circuit to generate at least one reconstructed input signal corresponding to a reconstructed version of the at least one filtered input signal based on the recovered data; and

a timing error circuit to generate at least one timing error signal indicative of a difference between the at least one filtered input signal and the at least one reconstructed input signal; and

a clock generator circuit to generate the sampling clock based on the at least one timing error signal.

2. The receiver of claim 1 , wherein the signal reconstruction circuit comprises a convolution circuit to generate the at least one reconstructed input signal by convolving the recovered data with target values.

3. The receiver of claim 1 , wherein the signal reconstruction circuit includes a look up table that references the recovered data to values of the at least one reconstructed input signal.

4. The receiver of claim 1 , wherein the timing error circuit generates the at least one timing error signal to be indicative of a gradient of a difference between the at least one filtered input signal and the at least one reconstructed input signal.

5. The receiver of claim 4 , wherein the timing error circuit comprises a minimum mean square estimator (MSME).

6. The receiver of claim 4 , wherein the timing error circuit generates at least one slope signal indicative of a slope of the at least one reconstructed input signal based on the at least one reconstructed input signal and generates the at least one timing error signal based on the at least one slope signal.

7. The receiver of claim 1 , wherein the feedback loop further comprises:

a loop filter circuit to filter the at least one timing error signal into at least one filtered timing error signal; and

a phase accumulator circuit to accumulate values of the at least one filtered timing error signal into at least one phase control signal,

wherein the clock generator adjusts a phase of the sampling clock based on the at least one phase control signal.

8. The receiver of claim 1 , wherein the clock generator circuit adjusts a phase of the sampling clock based on the at least one timing error signal.

9. A receiver comprising:

an analog to digital converter to convert an analog input signal into at least one digital input signal at timings controlled by a sampling clock;

a finite impulse response filter to generate at least one filtered input signal based on the at least one digital input signal;

a data decision circuit to generate recovered data based on the at least one filtered input signal; and

a feedback loop coupled to receive the at least one filtered input signal and to generate the sampling clock based on the at least one filtered input signal, the feedback loop comprising:

a timing error look up table that references the at least one filtered input signal and the recovered data to values for at least one timing error signal; and

a clock generator to generate the sampling clock based on the at least one timing error signal.

10. A method of operation in a receiver, the method comprising:

converting an analog input signal into at least one digital input signal at timings controlled by a sampling clock;

generating at least one filtered input signal based on the at least one digital input signal using a finite impulse response filter;

generating recovered data based on the at least one filtered input signal;

receiving the at least one filtered input signal and the recovered data at a feedback loop;

generating the sampling clock with the feedback loop based on the at least one filtered input signal and the recovered data, wherein generating the sampling clock comprises:

generating at least one reconstructed input signal corresponding to a reconstructed version of the at least one filtered input signal based on the recovered data; and

generating at least one timing error signal indicative of a difference between the at least one filtered input signal and the at least one reconstructed input signal; and

generating the sampling clock based on the at least one timing error signal.

11. The method of claim 10 , wherein generating the at least one reconstructed input signal comprises convolving the recovered data with target values.

12. The method of claim 10 , wherein the at least one timing error signal is generated to be indicative of a gradient of a difference between the at least one filtered input signal and the at least one reconstructed input signal.

13. The method of claim 12 , wherein generating the at least one timing error signal comprises generating at least one slope signal indicative of a slope of the at least one reconstructed input signal based on the at least one reconstructed input signal, and wherein generating the at least one timing error signal is based on the at least one slope signal.

14. The method of claim 10 , wherein generating the sampling clock based on the at least one timing error signal comprises:

filtering the at least one timing error signal into at least one filtered timing error signal;

accumulating values of the at least one filtered timing error signal into at least one phase control signal,

adjusting a phase of the sampling clock based on the at least one phase control signal.

15. The method of claim 10 , wherein generating the sampling clock based on the at least one timing error signal comprises adjusting a phase of the sampling clock based on the at least one timing error signal.

16. The method of claim 10 , wherein generating the at least one reconstructed input signal comprises looking up values in a look up table that references the recovered data to values of the at least one reconstructed input signal.