IP Library Granted Patent US 9,431,367
Granted Patent B2
US 9,431,367 · App. 14/503,932 · Granted Aug 30, 2016

Method of forming a semiconductor package

Inventors: Jing-Cheng Lin (Chu Tung Zhen, TW); Chin-Chuan Chang (Zhudong Township, TW); Jui-Pin Hung (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L24/83H01L21/4857H01L21/561H01L21/563H01L21/565H01L23/3128H01L23/3135H01L23/49816H01L23/49822H01L23/49827H01L23/49894H01L24/24H01L24/27H01L24/82H01L24/96H01L24/97H01L25/03H01L25/50H01L21/568H01L24/73H01L25/0657H01L2224/0401H01L2224/12105H01L2224/131H01L2224/32145H01L2224/32225H01L2224/45139H01L2224/48091H01L2224/48227H01L2224/73265H01L2224/82005H01L2224/8385H01L2224/83815H01L2224/97H01L2225/0651H01L2225/06568H01L2924/1305H01L2924/1306H01L2924/13091H01L2924/15311H01L2924/15331H01L2924/181
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Quick Facts
Patent No.
US 9,431,367
App. No.
14/503,932
Granted
Aug 30, 2016
Kind
B2
Abstract

A method of forming a semiconductor package includes forming an interconnecting structure on an adhesive layer, wherein the adhesive layer is on a carrier. The method further includes placing a semiconductor die on a surface of the interconnecting structure. The method further includes placing a package structure on the surface of the interconnecting structure, wherein the semiconductor die fits in a space between the interconnecting structure and the package structure. The method further includes performing a reflow to bond the package structure to the interconnecting structure.

Claims (44)

1. A method of forming a semiconductor package, the method comprising:

forming an interconnecting structure on an adhesive layer, wherein the adhesive layer is on a carrier;

placing a semiconductor die on a surface of the interconnecting structure;

placing a package structure on the surface of the interconnecting structure, wherein the semiconductor die fits in a space between the interconnecting structure and the package structure;

performing a reflow to bond the package structure to the interconnecting structure, wherein the reflow also bonds the semiconductor die to the interconnecting structure; and

covering the package structure and the semiconductor die with a molding layer, wherein the molding layer contacts a top surface of the semiconductor die and a bottom surface of the package structure.

2. A method of forming a semiconductor package, the method comprising:

forming an interconnecting structure on an adhesive layer, wherein the adhesive layer is on a carrier;

placing a semiconductor die on a surface of the interconnecting structure;

placing a package structure on the surface of the interconnecting structure, wherein the semiconductor die fits in a space between the interconnecting structure and the package structure;

performing a reflow to bond the package structure to the interconnecting structure;

performing another reflow after the semiconductor die is placed on the surface of the interconnecting structure and prior to placing the package structure; and

covering the package structure and the semiconductor die with a molding layer, wherein the molding layer contacts a top surface of the semiconductor die and a bottom surface of the package structure.

3. The method of claim 1 , wherein the interconnecting structure includes a redistribution layer (RDL), and wherein the RDL of the interconnecting structure enables fan-out connection of the semiconductor die.

4. The method of claim 1 , wherein the interconnecting structure includes a first contact to bond with the semiconductor die and a second contact to bond with the package structure, wherein the first contact is smaller than the second contact.

5. A method of making a semiconductor package, the method comprising:

forming an interconnecting structure, wherein the interconnecting structure includes a first redistribution layer (RDL) and a second RDL spaced from the first RDL, and the interconnecting structure has a thickness equal to or less than about 30 □m;

bonding a semiconductor die to the first RDL using a first bonding structure;

bonding the semiconductor die to the second RDL using a second bonding structure;

bonding a package structure to the first RDL using a third bonding structure; and

bonding the package structure to the second RDL using a fourth bonding structure, wherein the semiconductor die is between the package structure and the interconnecting structure.

6. The method of claim 5 , wherein bonding the semiconductor die to the first RDL is performed simultaneously with bonding the package structure to the first RDL.

7. The method of claim 5 , wherein bonding the semiconductor die to the first RDL is performed sequentially with bonding the package structure to the first RDL.

8. The method of claim 5 , further comprising applying a molding layer to cover the bonded package structure and the bonded semiconductor die.

9. The method of claim 8 , wherein applying the molding layer comprises filling a space between the semiconductor die and the interconnect structure.

10. The method of claim 5 , wherein forming the interconnect structure comprises:

forming the first RDL over a first passivation layer, wherein a portion of the first RDL extends through the first passivation layer, and the first passivation layer is over a carrier; and

forming the second RDL over the first passivation layer, wherein a portion of the second RDL extends through the first passivation layer.

11. The method of claim 10 , wherein forming the interconnect structure further comprises:

forming a first conductive layer over the first RDL, wherein the first conductive layer is electrically connected to the first RDL; and

forming a second conductive layer over the second RDL, wherein the second conductive layer is electrically connected to the first RDL.

12. The method of claim 11 , wherein bonding the package to the first RDL comprises bonding the package to the first RDL through the first conductive layer.

13. The method of claim 11 , wherein bonding the semiconductor die to the first RDL comprises bonding the semiconductor die to the first RDL through the first conductive layer.

14. The method of claim 10 , further comprising removing the carrier.

15. A method of making a semiconductor package, the method comprising:

forming an interconnecting structure, wherein the interconnecting structure comprises a first redistribution layer (RDL);

bonding a first semiconductor die to the first RDL using a first bonding structure having a first width; and

bonding a first package structure to the first RDL using a second bonding structure having a second width different from the first width, wherein the first package structure is on an opposite side of the first semiconductor die from the interconnecting structure, and an overall height of the semiconductor package ranges from about 350 microns (μm) to about 1050 μm.

16. The method of claim 15 , further comprising:

bonding a second semiconductor die to a second RDL using a first bonding structure having the first width, wherein the second RDL is in the interconnect structure; and

bonding a second package structure to the second RDL using a second bonding structure having the second width, wherein the second package structure is on an opposite side of the second semiconductor die from the interconnecting structure.

17. The method of claim 16 , further comprising forming a plurality of connecting elements on a side of the interconnect opposite the first semiconductor die and the second semiconductor die, wherein a first connecting element of the plurality of connecting elements is electrically connected to the first semiconductor die, and a second connecting element of the plurality of connecting elements is electrically connected to the second semiconductor die.

18. The method of claim 16 , further comprising sawing the semiconductor package to separate the first semiconductor die and the first package structure from the second semiconductor die and the second package structure.

19. The method of claim 15 , further comprising applying a molding layer to cover the bonded first package structure and the bonded first semiconductor die.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 1, 2014
From: LIN, JING-CHENG; CHANG, CHIN-CHUAN; HUNG, JUI-PIN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 033864/0129 →
Continuity (2)
Division 13597868 · Aug 29, 2012
Related Publication 20150017764A1 · Jan 15, 2015