Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation
Semiconductor-oxide-containing gate dielectrics can be formed on surfaces of semiconductor fins prior to formation of a disposable gate structure. A high dielectric constant (high-k) dielectric spacer can be formed to protect each semiconductor-oxide-containing gate dielectric. Formation of the high-k dielectric spacers may be performed after formation of gate cavities by removal of disposable gate structures, or prior to formation of disposable gate structures. The high-k dielectric spacers can be used as protective layers during an anisotropic etch that vertically extends the gate cavity, and can be removed after vertical extension of the gate cavities. A subset of the semiconductor-oxide-containing gate dielectrics can be removed for formation of high-k gate dielectrics for first type devices, while another subset of the semiconductor-oxide-containing gate dielectrics can be employed as gate dielectrics for second type devices. The vertical extension of the gate cavities increases channel widths in the fin field effect transistors.
1. A semiconductor structure comprising:
a semiconductor fin located on a substrate;
a shallow trench isolation layer in contact with sidewalls of a lower portion of said semiconductor fin;
a semiconductor-oxide-containing gate dielectric in contact with sidewalls of an upper portion of said semiconductor fin; and
a gate electrode straddling said semiconductor fin and overlying said semiconductor-oxide-containing gate dielectric, wherein a portion of said gate electrode protrudes downward into a recess within said shallow trench isolation layer, and is laterally spaced from said lower portion of said semiconductor fin by a vertical portion of said shallow trench isolation layer.
2. The semiconductor structure of claim 1 , further comprising a high dielectric constant gate dielectric having a dielectric constant greater than 8.0 and in contact with a top surface and outer sidewalls of said semiconductor-oxide-containing gate dielectric and a sidewall surface of said vertical portion of said shallow trench isolation layer and a recessed horizontal surface of said shallow trench isolation layer.
3. The semiconductor structure of claim 2 , further comprising:
another semiconductor fin located on said substrate; and
another high dielectric constant gate dielectric located on sidewalls of said another semiconductor fin and having a same composition as, and a same thickness as, said high dielectric constant gate dielectric.
4. The semiconductor structure of claim 3 , wherein said shallow trench isolation layer further includes another recessed portion having a horizontal recessed surface that is located below a horizontal plane including a recessed surface of said shallow trench isolation layer that underlies said gate electrode.
5. The semiconductor structure of claim 1 , wherein said vertical portion of said shallow trench isolation layer differs from said semiconductor-oxide-containing gate dielectric by at least one of composition and thickness, and each sidewall of said upper portion of said semiconductor fin is vertically coincident with a sidewall of said lower portion of said semiconductor fin.
6. A semiconductor structure comprising:
a semiconductor fin located on a substrate;
a semiconductor-oxide-containing gate dielectric in contact with sidewalls of said semiconductor fin and a top surface of said substrate;
a high dielectric constant dielectric liner having a dielectric constant greater than 8.0 and contacting, and laterally surrounding, a lower portion of said semiconductor-oxide-containing gate dielectric;
a shallow trench isolation layer laterally surrounding a portion of said high dielectric constant dielectric liner; and
a gate electrode straddling said semiconductor fin and overlying said semiconductor-oxide-containing gate dielectric and said high dielectric constant dielectric liner, wherein a portion of said gate electrode protrudes downward into a recess within said shallow trench isolation layer.
7. The semiconductor structure of claim 6 , further comprising a high dielectric constant gate dielectric having a dielectric constant greater than 8.0 and in contact with a top surface and outer sidewalls of said semiconductor-oxide-containing gate dielectric, a topmost surface of said high dielectric constant dielectric liner, and a recessed horizontal surface of said shallow trench isolation layer.
8. The semiconductor structure of claim 6 , further comprising:
another semiconductor fin located on said substrate; and
another high dielectric constant gate dielectric located on sidewalls of said another semiconductor fin and having a same composition as, and a same thickness as, said high dielectric contact gate dielectric.
9. The semiconductor structure of claim 8 , further comprising:
a semiconductor-oxide-containing dielectric portion contacting, and laterally surrounding, a lower portion of said another semiconductor fin and having a same thickness as said semiconductor-oxide-containing gate dielectric; and
another high dielectric constant dielectric liner having a same composition as, and a same thickness as, said high dielectric constant dielectric liner and contacting, and laterally surrounding, said semiconductor-oxide-containing portion.
10. The semiconductor structure of claim 8 , further comprising a semiconductor-oxide-containing dielectric portion contacting, and laterally surrounding, a lower portion of said another semiconductor fin and having a same thickness as said semiconductor-oxide-containing gate dielectric, wherein said high dielectric constant dielectric liner laterally surrounds said semiconductor-oxide-containing portion.