IP Library › Granted Patent US 9,431,398
Granted Patent B2
US 9,431,398 · App. 14/262,830 · Granted Aug 30, 2016

Semiconductor chip having a circuit with cross-coupled transistors to thwart reverse engineering

Inventor: Thomas Kuenemund (Munich, DE)
Assignee: INFINEON TECHNOLOGIES AG
H01L27/092H01L23/528H01L23/576H01L2924/0002
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Quick Facts
Patent No.
US 9,431,398
App. No.
14/262,830
Granted
Aug 30, 2016
Kind
B2
Abstract

According to one embodiment, a chip has a circuit with at least one p channel field effect transistor (FET); at least one n channel FET; a first and a second power supply terminal; wherein the n channel FET, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the p channel FET; and the p channel FET, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the n channel FET; wherein the logic state of the gate of the p channel FET and of the n channel FET can only be changed by at least one of the first and second supply voltage to the circuit; and a connection coupled to the gate of the p channel FET or the n channel FET and a further component of the semiconductor chip.

Claims (77)

1. A semiconductor chip comprising:

a circuit comprising

a plurality of p channel field effect transistors wherein the p channel field effect transistors are connected in series and their gates are connected;

a plurality of n channel field effect transistors wherein the n channel field effect transistors are connected in series and their gates are connected;

a first power supply terminal configured to receive a first supply voltage with an upper supply potential; and

a second power supply terminal configured to receive a second supply voltage with a lower supply potential;

wherein the p channel field effect transistors and the n channel field effect transistors are connected such that

the n channel field effect transistors, if supplied with the upper supply potential at their gates, supply the lower supply potential to the gates of the p channel field effect transistors; and

the p channel field effect transistors, if supplied with the lower supply potential at their gates, supply the upper supply potential to the gates of the n channel field effect transistors;

wherein the circuit is configured such that the logic state of the gates of the p channel field effect transistors and the logic state of the gates of the n channel field effect transistors can only be changed by changing a supply of at least one of the first supply voltage and the second supply voltage to the circuit; and

a connection coupled to the gates of the p channel field effect transistors or the gates of the n channel field effect transistors and a further component of the semiconductor chip.

2. A semiconductor chip comprising:

a circuit comprising

at least one p channel field effect transistor;

at least one n channel field effect transistor;

a first power supply terminal configured to receive a first supply voltage with an upper supply potential; and

a second power supply terminal configured to receive a second supply voltage with a lower supply potential;

wherein the at least one p channel field effect transistor and the at least one n channel field effect transistor are connected such that

the at least one n channel field effect transistor, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the at least one p channel field effect transistor; and

the at least one p channel field effect transistor, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the at least one n channel field effect transistor;

wherein the circuit is configured such that the logic state of the gate of the at least one p channel field effect transistor and the logic state of the gate of the at least one n channel field effect transistor can only be changed by changing a supply of at least one of the first supply voltage and the second supply voltage to the circuit; and

a connection coupled to the gate of the at least one p channel field effect transistor or the gate of the at least one n channel field effect transistor and a dummy gate or a metal fill structure of the semiconductor chip.

3. The semiconductor chip according to claim 2 , wherein the connection is configured to supply the logic state of the gate of the at least one p channel field effect transistor to the dummy gate or metal fill structure of the semiconductor chip.

4. The semiconductor chip according to claim 2 , comprising a first connection coupled to the gate of the at least one p channel field effect transistor and a first further component of the semiconductor chip and a second connection coupled to the gate of the at least one n channel field effect transistor and a second further component of the semiconductor chip.

5. The semiconductor chip according to claim 2 , wherein the circuit comprises:

a plurality of p channel field effect transistors;

wherein the p channel field effect transistors and the at least one n channel field effect transistor are connected such that

the at least one n channel field effect transistor, if supplied with a upper supply potential at its gate, supplies the lower supply potential to the gates of the p channel field effect transistors; and

the p channel field effect transistors, if supplied with the lower supply potential at their gates, supply the upper supply potential to the gate of the at last one n channel field effect transistor;

wherein the circuit is configured such that the logic state of the gate of the p channel field effect transistors can only be changed by changing a supply of at least one of the first supply voltage and the second supply voltage to the circuit; and

wherein the semiconductor chip further comprises a connection coupled to the gate of the p channel field effect transistors or the gate of the at least one n channel field effect transistor and the dummy gate or metal fill structure of the semiconductor chip.

6. The semiconductor chip according to claim 2 , wherein the circuit comprises:

a plurality of n channel field effect transistors;

wherein the n channel field effect transistors and the at least one p channel field effect transistor are connected such that

the at least one p channel field effect transistor, if supplied with a lower supply potential at its gate, supplies the higher supply potential to the gates of the n channel field effect transistors; and

the n channel field effect transistors, if supplied with the higher supply potential at their gates, supply the lower supply potential to the gate of the at last one p channel field effect transistor;

wherein the circuit is configured such that the logic state of the gate of the n channel field effect transistors can only be changed by changing a supply of at least one of the first supply voltage and the second supply voltage to the circuit; and

wherein the semiconductor chip further comprises a connection coupled to the gate of the n channel field effect transistors or the gate of the at least one p channel field effect transistor and the dummy gate or metal fill structure of the semiconductor chip.

7. The semiconductor chip according to claim 2 , wherein the circuit comprises:

a plurality of p channel field effect transistors;

a plurality of n channel field effect transistors;

wherein the p channel field effect transistors and the n channel field effect transistors are connected such that

the n channel field effect transistors, if supplied with a upper supply potential at their gates, supply the lower supply potential to the gates of the p channel field effect transistors; and

the p channel field effect transistors, if supplied with the lower supply potential at their gates, supply the upper supply potential to the gates of the n channel field effect transistors;

wherein the circuit is configured such that the logic state of the gates of the p channel field effect transistors and the logic state of the gates of the n channel field effect transistors can only be changed by changing a supply of at least one of the first supply voltage and the second supply voltage to the circuit; and

wherein the semiconductor chip further comprises a connection coupled to the gates of the p channel field effect transistors or the gates of the n channel field effect transistors and the dummy gate or metal fill structure of the semiconductor chip.

8. The semiconductor chip according to claim 7 , wherein the p channel field effect transistors are connected in series and their gates are connected and the n channel field effect transistors are connected in series and their gates are connected.

9. The semiconductor chip according to claim 2 , comprising a multiplicity of circuits, each circuit comprising

at least one p channel field effect transistor;

at least one n channel field effect transistor;

a first power supply terminal configured to receive the first supply voltage with the upper supply potential;

a second power supply terminal configured to receive the second supply voltage with the lower supply potential;

wherein the at least one p channel field effect transistor and the at least one n channel field effect transistor are connected such that

the at least one n channel field effect transistor, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the at least one p channel field effect transistor; and

the at least one p channel field effect transistor, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the at least one n channel field effect transistor;

wherein the circuit is configured such that the logic state of the gate of the at least one p channel field effect transistor and the logic state of the gate of the at least one n channel field effect transistor can only be changed by changing a supply of at least one of the first supply voltage and the second supply voltage to the circuit; and

the semiconductor chip comprises a connection coupled to the gate of the at least one p channel field effect transistor or the gate of the at least one n channel field effect transistor and a dummy gate or a metal fill structure of the semiconductor chip.

10. The semiconductor chip according to claim 2 , further comprising a second circuit comprising

at least one p channel field effect transistor;

at least one n channel field effect transistor;

a first power supply terminal configured to receive the first supply voltage with the upper supply potential;

a second power supply terminal configured to receive the second supply voltage with the lower supply potential;

wherein the at least one p channel field effect transistor and the at least one n channel field effect transistor are connected such that

the at least one n channel field effect transistor, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the at least one p channel field effect transistor; and

the at least one p channel field effect transistor, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the at least one n channel field effect transistor;

wherein the circuit is configured such that the logic state of the gate of the at least one p channel field effect transistor and the logic state of the gate of the at least one n channel field effect transistor can only be changed by changing a supply of at least one of the first supply voltage and the second supply voltage to the circuit; and

wherein the gate of the at least one p channel field effect transistor and the gate of the at least one n channel field effect transistor are electrically isolated from any further components of the semiconductor chip.

11. The semiconductor chip according to claim 2 , wherein the circuit further comprises

at least one second p channel field effect transistor;

at least one second n channel field effect transistor;

wherein the at least one second p channel field effect transistor and the at least one second n channel field effect transistor are connected such that

the at least one second n channel field effect transistor, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the at least one second p channel field effect transistor; and

the at least one second p channel field effect transistor, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the at least one second n channel field effect transistor;

and wherein further at least one of

the at least one second n channel field effect transistor, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the at least one p channel field effect transistor; and

the at least one second p channel field effect transistor, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the at least one n channel field effect transistor.

12. The semiconductor chip according to claim 11 , wherein the circuit is configured such that the logic state of the gate of the at least one second p channel field effect transistor and the logic state of the gate of the at least one second n channel field effect transistor can only be changed by changing a supply of at least one of the first supply voltage and the second supply voltage to the circuit.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF THE RECEIVING PARTY PREVIOUSLY RECORDED AT REEL: 032764 FRAME: 0676. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 29, 2016
From: KUENEMUND, THOMAS
To: INFINEON TECHNOLOGIES AG
Reel/Frame 039515/0092 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2014
From: KUENEMUND, THOMAS
To: INFINEON THECHNOLOGIES AG
Reel/Frame 032764/0676 →
Continuity (1)
Related Publication 20150311202A1 · Oct 29, 2015