Patterning of vertical nanowire transistor channel and gate with directed self assembly

1. A method of forming a nanowire transistor on a substrate, the method comprising:

forming a guide opening in a mask layer disposed over a dielectric layer disposed over a doped semiconductor layer disposed over a substrate;

depositing a directed self-assembly (DSA) material into the guide opening;

segregating the DSA material into an interior polymer region completely surrounded by an exterior polymer region within the guide opening, the interior polymer region having a cylindrical geometry having a diameter;

removing the interior polymer region selectively to the exterior polymer region;

forming a trench in the dielectric layer and the doped semiconductor layer wherein the trench has a diameter defined by the diameter of the cylindrical geometry of the interior polymer region;

removing the mask layer and a peripheral portion of the dielectric layer beneath the mask layer to form an annular portion of the dielectric layer surrounding the trench;

removing the exterior polymer region;

depositing a first source/drain semiconductor material in the trench;

depositing a channel semiconductor material on the first source/drain semiconductor material in the trench;

depositing a second source/drain semiconductor material on the channel semiconductor material in the trench;

removing at least a portion of the annular portion of the dielectric layer surrounding the trench to form a gate trench surrounding the channel semiconductor material;

depositing a gate dielectric in the gate trench adjacent to and surrounding the channel semiconductor material; and

depositing a gate electrode in the gate trench adjacent the gate dielectric layer in the gate trench and surrounding the channel semiconductor material.

2. The method of claim 1 wherein removing at least a portion of the annular portion of the dielectric layer comprises removing all of the annular portion of the dielectric layer.

3. The method of claim 1 wherein removing at least a portion of annular portion of the dielectric layer comprises removing only a portion of the annular portion of the dielectric layer and leaving a lower portion of the annular portion of the dielectric layer and wherein forming the gate dielectric layer comprises forming the gate dielectric layer on the lower portion of the annular portion of the dielectric layer.

4. The method of claim 1 wherein forming the guide opening comprises lithographically patterning a curved guide.

5. The method of claim 1 wherein forming the guide opening comprises lithographically patterning a circular guide opening.

6. The method of claim 1 wherein segregating the DSA material comprises baking and/or curing the DSA material.

7. The method of claim 1 further comprising polishing the second source/drain semiconductor material so that the second source/drain semiconductor material in the trench is planar with a top surface of the annular portion of the dielectric layer.

8. The method of claim 1 , wherein depositing the DSA material into the guide opening further comprises spin coating a DSA material comprising first and second polymeric materials; and

wherein segregating the DSA material further comprises curing the DSA material at a temperature and for a duration sufficient to permit the first polymeric material to migrate into the interior polymer portion while the second polymeric material migrates into the exterior polymer portion.

9. The method of claim 8 , wherein one of the first and second polymeric materials comprises PMMA.

10. The method of claim 9 , wherein the other of the first and second polymeric material comprises polystyrene.

11. The method of claim 8 , wherein the mask layer comprises one of the first and second polymeric materials.