Nonvolatile charge trap memory device having a high dielectric constant blocking region
An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the split charge-trapping region. The split charge-trapping region includes a first charge-trapping layer comprising a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The multi-layer blocking dielectric comprises at least a high-K dielectric layer.
1. A memory device comprising:
a channel electrically connecting a first diffusion region and a second diffusion region of the memory device; and
a gate stack adjoining at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a charge-trapping layer abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the charge-trapping layer,
wherein the charge-trapping layer includes a first charge-trapping layer comprising an oxygen-rich nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a silicon-rich nitride overlying the first charge-trapping layer, and
wherein the multi-layer blocking dielectric comprises a first dielectric layer abutting the charge-trapping layer comprising an oxidized portion of the second charge-trapping layer and a second dielectric layer abutting the first dielectric layer, the first dielectric layer having a dielectric constant in the range of 3.5-4.5, and the second dielectric layer comprising a silicate and having a dielectric constant higher than a dielectric constant of the first dielectric layer.
2. The memory device of claim 1 , wherein the second dielectric layer comprises hafnium silicate.
3. The memory device of claim 1 , wherein the second dielectric layer comprises zirconium silicate.
4. The memory device of claim 1 , further comprising a gate layer disposed above the second dielectric layer, and wherein the gate layer is a high work-function gate layer.
5. A memory device comprising:
a channel electrically connecting a first diffusion region and a second diffusion region of the memory device; and
a gate stack adjoining at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a charge-trapping layer abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the charge-trapping layer,
wherein the charge-trapping layer includes a first charge-trapping layer comprising an oxygen-rich nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a silicon-rich nitride overlying the first charge-trapping layer, and
wherein the multi-layer blocking dielectric comprises a first dielectric layer abutting the charge-trapping layer comprising an oxidized portion of the second charge-trapping layer and a second dielectric layer abutting the first dielectric layer, the first dielectric layer having a dielectric constant in the range of 3.5-4.5, and the second dielectric layer comprising a silicate and having a dielectric constant higher than a dielectric constant of the first dielectric layer, and
further comprising a polysilicon gate layer doped with a p-type dopant abutting the multi-layer blocking dielectric.
6. The memory device of claim 5 , wherein the second dielectric layer comprises hafnium silicate.
7. The memory device of claim 5 , wherein the second dielectric layer comprises zirconium silicate.