Oxide film scheme for RRAM structure
The present disclosure relates to a method of forming an RRAM cell having a dielectric data layer that provides good performance, device yield, and data retention, and an associated apparatus. In some embodiments, the method is performed by forming an RRAM film stack having a bottom electrode layer disposed over a semiconductor substrate, a top electrode layer, and a dielectric data storage layer disposed between the bottom electrode and the top electrode. The dielectric data storage layer has a performance enhancing layer with a hydrogen-doped oxide and a data retention layer having an aluminum oxide. The RRAM film stack is then patterned according to one or more masking layers to form a top electrode and a bottom electrode, and an upper metal interconnect layer is formed at a position electrically contacting the top electrode.
1. An RRAM (resistive random access memory) cell, comprising:
a bottom electrode disposed over a semiconductor substrate;
a dielectric data storage layer disposed over the bottom electrode, and comprising:
a performance enhancing layer including a hydrogen-doped oxide contacting the bottom electrode; and
a data retention layer comprising a hafnium aluminum oxide layer contacting the performance enhancing layer and including a stacked structure that alternates between layers of hafnium oxide and layers of aluminum oxide; and
a top electrode disposed over the dielectric data storage layer.
2. The RRAM cell of claim 1 ,
wherein the performance enhancing layer comprises a hydrogen-doped hafnium oxide (HfOx) layer.
3. The RRAM cell of claim 2 , wherein the hafnium aluminum oxide (HfAlO x ) layer has an aluminum content in a range of between approximately 30% and approximately 65%.
4. The RRAM cell of claim 2 ,
wherein the hydrogen-doped hafnium oxide (HfO x ) layer has a first thickness in a range of between approximately 5 angstroms (Å) and approximately 40 Å; and
wherein the hafnium aluminum oxide (HfAlO x ) layer has a second thickness in a range of between approximately 10 Å and approximately 40 Å.
5. The RRAM cell of claim 1 , wherein the data retention layer is disposed onto and in direct contact with a top surface of the performance enhancing layer.
6. The RRAM cell of claim 1 , wherein the data retention layer comprises a hydrogen-doped hafnium aluminum oxide (HfAlO x ) layer.
7. An RRAM (resistive random access memory) cell, comprising:
a bottom electrode disposed over a semiconductor substrate;
a dielectric data storage layer disposed over the bottom electrode and having a variable resistance, wherein the dielectric data storage layer comprises a performance enhancing layer including a hydrogen-doped oxide and an overlying data retention layer comprising a stacked structure that alternates between layers of hafnium oxide and layers of aluminum oxide;
a cap layer arranged over the dielectric data storage layer; and
a top electrode arranged over the cap layer.
8. The RRAM cell of claim 7 , wherein the performance enhancing layer comprises hydrogen-doped oxide.
9. The RRAM cell of claim 8 , wherein the data retention layer comprises hafnium aluminum oxide.
10. The RRAM cell of claim 9 , wherein an aluminum content of the data retention layer is in a range of between approximately 30% and approximately 65%.
11. The RRAM cell of claim 9 , wherein the stacked structure comprises alternating layers of aluminum oxide and hafnium oxide.
12. The RRAM cell of claim 11 , wherein the stacked structure comprises a first number of layers of aluminum oxide and a second number of layers of hafnium oxide that is greater than the first number.
13. The RRAM cell of claim 11 , wherein the data retention layer has a lower surface facing the performance enhancing layer, which comprises a hafnium oxide layer.
14. The RRAM cell of claim 8 , wherein the data retention layer comprises hydrogen doped hafnium aluminum oxide.
15. The RRAM cell of claim 7 , wherein the data retention layer has a thickness that is greater than or equal to a thickness of the performance enhancing layer.
16. The RRAM cell of claim 7 , further comprising:
a masking layer disposed over the top electrode; and
an upper metal via extending through the masking layer to the top electrode.
17. The RRAM cell of claim 7 , wherein the performance enhancing layer contacts an upper surface of the bottom electrode and the data retention layer contacts a lower surface of the cap layer.
18. The RRAM cell of claim 7 ,
wherein the performance enhancing layer and the data retention layer have sidewalls that are aligned with one another and that are laterally offset from sidewalls of the top electrode; and
wherein the cap layer has sidewalls that are offset from the sidewalls of the data retention layer.
19. An RRAM (resistive random access memory) cell, comprising:
a bottom electrode disposed over a semiconductor substrate;
a hydrogen-doped hafnium oxide layer disposed onto the bottom electrode;
a hafnium aluminum oxide layer disposed onto and in direct contact with a top surface of the hydrogen-doped hafnium oxide layer; and
a top electrode arranged over the hafnium aluminum oxide layer.
20. The RRAM cell of claim 19 , further comprising:
a cap layer arranged onto and in direct contact with the hafnium aluminum oxide layer.