Semiconductor device with nonvolatile memory prevented from malfunctioning caused by momentary power interruption
In an internal register, a value for controlling operation of a flash memory is stored. A power shutoff detection register holds a value which changes when power shutoff occurs, and data stored in a specific memory cell is written in the power shutoff detection register. An EX-OR circuit compares the data stored in the specific memory cell with the value of the power shutoff detection register to thereby detect power shutoff. When power shutoff is detected, the value of the internal register is re-set. Thus, when power shutoff occurs, the flash memory can be prevented from malfunctioning.
1. A semiconductor device including a nonvolatile memory, comprising:
an internal register storing a value for controlling an operation of said nonvolatile memory;
a power shutoff detection register holding a value which changes when power shutoff occurs, configured of a latch circuit holding a value which is more prone to change than the value held in said internal register when power shutoff occurs and including a plurality of P- channel MOS transistors and a plurality of N-channel MOS transistors, configured so that a specific P-channel MOS transistor and a specific N-channel MOS transistor among said plurality of P-channel MOS transistors and said plurality of N-channel MOS transistors have a greater gate width than that of the other P-channel MOS transistor and the other N-channel MOS transistor to have an enhanced drive ability and accordingly a value held in the power shutoff detection register is more prone to change when power shutoff occurs; and
a controller for controlling the operation of said nonvolatile memory in accordance with the value stored in said internal register, wherein said controller re-sets the value of said internal register when said controller detects power shutoff based on a change of the value held in said power shutoff detection register.
2. The semiconductor device according to claim 1 , wherein said controller notifies outside of an occurrence of power shutoff when said controller detects the power shutoff based on a change of the value held in said power shutoff detection register, and re-sets the value of said internal register in accordance with a reset instruction from outside.
3. The semiconductor device according to claim 1 , wherein said controller sets, in said power shutoff detection register, data which is stored in a specific memory cell of said nonvolatile memory, and compares the data stored in said specific memory cell with the value stored in said power shutoff detection register to thereby detect power shutoff.
4. The semiconductor device according to claim 1 , further comprising a second nonvolatile memory, wherein: said controller sets, in said power shutoff detection register, data which is stored at a specific address of said second nonvolatile memory, and compares the data stored at said specific address with the value stored in said power shutoff detection register to thereby detect power shutoff.
5. The semiconductor device according to claim 1 , further comprising an address latch circuit storing an address for selecting a memory cell of said nonvolatile memory, wherein: said power shutoff detection register is configured of a latch circuit holding a value which is more prone to change than a value held in said address latch circuit when power shutoff occurs.
6. A semiconductor device including a nonvolatile memory, comprising:
an internal register storing a value for controlling an operation of said nonvolatile memory;
a power shutoff detection register holding a value which changes when power shutoff occurs, configured of a latch circuit holding a value which is more prone to change than the value held in said internal register when power shutoff occurs and including a plurality of P-channel MOS transistors and a plurality of N-channel MOS transistors, configured so that a specific P-channel MOS transistor and a specific N-channel MOS transistor among said plurality of P-channel MOS transistors and said plurality of N-channel MOS transistors have a greater gate width than that of the other P-channel MOS transistor and the other N-channel MOS transistor to have an enhanced drive ability and accordingly a value held in the power shutoff detection register is more prone to change when power shutoff occurs; and
a controller for controlling the operation of said nonvolatile memory in accordance with the value stored in said internal register, wherein said controller stops a data rewrite operation for said nonvolatile memory, when said controller detects power shutoff based on a change of the value held in said power shutoff detection register while said data rewrite operation is performed.
7. The semiconductor device according to claim 6 , wherein said controller stops the data rewrite operation and thereafter re-sets the value of said internal register to re-execute the data rewrite operation.
8. A semiconductor device including a processor and a nonvolatile memory, comprising:
an internal register storing a value for controlling an operation of said nonvolatile memory;
a power shutoff detection register holding a value which changes when power shutoff occurs, configured of a latch circuit holding a value which is more prone to change than the value held in said internal register when power shutoff occurs and including a plurality of P-channel MOS transistors and a plurality of N-channel MOS transistors, configured so that a specific P-channel MOS transistor and a specific N-channel MOS transistor among said plurality of P-channel MOS transistors and said plurality of N-channel MOS transistors have a greater gate width than that of the other P-channel MOS transistor and the other N-channel MOS transistor to have an enhanced drive ability and accordingly a value held in the power shutoff detection register is more prone to change when power shutoff occurs; and
a controller for controlling the operation of said nonvolatile memory in accordance with the value stored in said internal register, wherein said controller stops a data rewrite operation for said nonvolatile memory, when said controller detects power shutoff based on a change of the value held in said power shutoff detection register while said data rewrite operation is performed, and notifying said processor of occurrence of the power shutoff.
9. The semiconductor device according to claim 8 , wherein when said processor is notified of occurrence of the power shutoff by said controller, said processor re-issues a rewrite command to said controller to cause said controller to rewrite data.
10. The semiconductor device according to claim 8 , wherein: said processor issues a power shutoff detection command to said controller, and when said controller receives the power shutoff detection command from said processor, said controller detects power shutoff based on a change of the value held in said power shutoff detection register.