IP Library Granted Patent US 9,437,545
Granted Patent B2
US 9,437,545 · App. 14/569,342 · Granted Sep 6, 2016

Interconnects having sealing structures to enable selective metal capping layers

Inventors: Jun He (Phoenix, AZ); Kevin J. Fischer (Hillsboro, OR); Ying Zhou (Tigard, OR); Peter K. Moon (Portland, OR)
Assignee: Intel Corporation
H01L23/53209H01L21/0217H01L21/02252H01L21/32053H01L21/76802H01L21/76834H01L21/76844H01L21/76849H01L21/76856H01L21/76877H01L21/76888H01L23/5283H01L23/5329H01L23/53238H01L2924/0002
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Quick Facts
Patent No.
US 9,437,545
App. No.
14/569,342
Granted
Sep 6, 2016
Kind
B2
Abstract

Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.

Claims (19)

1. A method of fabricating an interconnect structure, comprising:

providing an interconnect including a conductive material extending into a dielectric material layer;

forming capping layer proximate said interconnect;

forming a sealing structure to seal at least one gap of exposed interconnect conductive material between said capping layer and said dielectric layer; and

exposing the exposed interconnect conductive material to silane to form a first salicide layer; and

exposing the first salicide layer to an ammonia source to form a silicon nitride layer.

2. The method of claim 1 , wherein forming the sealing structure comprises:

exposing an exposed surface of the capping layer to silane to form a second salicide layer; and

exposing the second salicide layer to the ammonia source to form the silicon nitride layer.

3. The method of claim 2 , wherein said sealing structure comprises the silicon nitride layer that is different than the capping material layer.

4. The method of claim 2 , wherein the first silicide layer is formed at a different rate than the second silicide layer.

5. A method of fabricating an interconnect structure, comprising:

providing a dielectric material layer;

forming an opening within said dielectric material layer;

forming a barrier material layer on at least one sidewall and bottom of said opening;

disposing a conductive material within said opening and abutting said barrier material layer;

forming capping layer proximate said conductive material;

forming a sealing structure to seal at least one gap of exposed conductive material between said capping layer and said dielectric layer, wherein forming said sealing structure comprises forming a salicide in portions of a conductive material of said interconnect by exposure to silane and exposing said salicide to an ammonia source to form a silicon nitride layer.

6. The method of claim 5 , wherein the sealing structure comprises the silicon nitride layer that is different than the capping material layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2022
From: INTEL CORPORATION
To: TAHOE RESEARCH, LTD.
Reel/Frame 061175/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2015
From: HE, JUN; FISCHER, KEVIN J.; ZHOU, YING; MOON, PETER K.
To: INTEL CORPORATION
Reel/Frame 036627/0536 →
Continuity (4)
Division 13242988 · Sep 23, 2011
Division 12079683 · Mar 28, 2008
Division 11144576 · Jun 3, 2005
Related Publication 20150097292A1 · Apr 9, 2015