Semiconductor chip with redundant thru-silicon-vias
A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.
1. A method of manufacturing, comprising:
forming a first plurality of conductive vias in a layer of a first semiconductor chip, the first plurality of conductive vias including first ends and second ends;
forming conductive via extensions on each of the first ends of the first conductive vias; and
forming a first conductor pad in ohmic contact with the conductive via extensions.
2. The method of claim 1 , comprising forming a second plurality of conductive vias in the layer, the second plurality of conductive vias including third ends and fourth ends, and forming a second conductor pad in ohmic contact with the third ends.
3. The method of claim 1 , comprising forming a conductor structure in ohmic contact with the second ends of the first plurality of conductive vias.
4. The method of claim 3 , wherein the conductor structure comprises a redistribution layer structure.
5. The method of claim 1 , comprising coupling an input/out structure to the first conductor pad.
6. The method of claim 5 , wherein the input/output structure comprises a solder bump or a conductive pillar.
7. The method of claim 1 , comprising stacking a second semiconductor chip on the first semiconductor chip.
8. The method of claim 1 , comprising mounting the first semiconductor chip on a circuit board.
9. The method of claim 1 , wherein the first plurality of conductive vias are formed by forming trenches in the first semiconductor chip and placing conductor material in the trenches.
10. The method of claim 1 , wherein the first conductive vias include a polymer core and a conductor jacket around the polymer core.
11. A method of manufacturing, comprising:
forming a first plurality of conductive vias in a layer of a first semiconductor chip, the first plurality of conductive vias including first ends and second ends, the first semiconductor chip having a first side and a second and opposite side;
forming conductive via extensions on each of the first ends of the first conductive vias;
forming a first conductor structure proximate the first side and in ohmic contact with the conductive via extensions; and
forming a second conductor proximate the second side and in ohmic contact with the second ends of the first plurality of conductive vias.
12. The method of claim 11 , wherein the first conductor comprises a conductor pad and the second conductor comprises a redistribution layer structure.
13. The method of claim 11 , comprising coupling an input/output structure to the first conductor.
14. The method of claim 13 , wherein the input/output structure comprises a solder bump or a conductive pillar.
15. The method of claim 11 , comprising stacking a second semiconductor chip on the first semiconductor chip.
16. The method of claim 11 , wherein the first conductive vias include a polymer core and a conductor jacket around the polymer core.
17. A method of manufacturing, comprising:
forming a first plurality of conductive vias in a layer of a first semiconductor chip, the first plurality of conductive vias including first ends, second ends, a polymer core and a conductor jacket around the polymer core; and
forming a first conductor pad in ohmic contact with the first ends of the first conductive vias.