IP Library Granted Patent US 9,443,766
Granted Patent B2
US 9,443,766 · App. 15/009,045 · Granted Sep 13, 2016

Method for manufacturing diode

Inventors: Toru Onishi (Nagoya, JP); Yuichiro Matsuura (Toyota, JP)
Assignee: Toyota Jidosha Kabushiki Kaisha
H01L21/8222H01L21/266H01L27/0716H01L29/6609H01L29/66348
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Quick Facts
Patent No.
US 9,443,766
App. No.
15/009,045
Granted
Sep 13, 2016
Kind
B2
Abstract

A diode manufacturing method provided herein includes first-third implantations and a heating. The first implantation implants n-type impurities into a first range at a first depth. The second implantation implants n-type impurities into a second range including the first range as a part at a second depth shallower than the first depth. The third implantation implants p-type impurities into a third range located on both sides of the second range at a third depth shallower than the first depth at a density higher than the second implantation. The semiconductor substrate is heated in the heating so that a first p-type region (contact region) is formed in the implanted region in the third implantation and a first n-type region (pillar region) is formed in a part of the implanted region in the first and second implantations.

Claims (29)

1. A method for manufacturing a diode that comprises:

an anode electrode;

a contact region being of p-type and in contact with the anode electrode;

a body region being of p-type, located on a lower side of the contact region, and having a density of p-type impurities lower than that in the contact region;

a barrier region being of n-type and located on a lower side of the body region; and

a pillar region being of n-type and extending from a position being in contact with the anode electrode to the barrier region by penetrating the contact region and the body region,

the method comprising:

providing a first implantation in which n-type impurities are implanted into a first range of an upper surface of a semiconductor substrate at a first depth;

providing a second implantation in which the n-type impurities are implanted into a second range of the upper surface at a second depth, the second range including the first range as a part, and the second depth being shallower than the first depth;

providing a third implantation in which the p-type impurities are implanted into a third range of the upper surface at a third depth at a density higher than a density of the n-type impurities implanted in the second implantation, the third range being located on both sides of the second range, and the third depth being shallower than the first depth; and

providing a first heating in which the semiconductor substrate is heated so that a first p-type region is formed in a region into which the p-type impurities were implanted in the third implantation and a first n-type region is formed in a part of a region into which the n-type impurities were implanted in the first and second implantations,

wherein

the first p-type region serves as the contact region, and the first n-type region serves as the pillar region.

2. The method of claim 1 , further comprising:

providing a fourth implantation in which the p-type impurities are implanted into a fourth range of the upper surface at a fourth depth, the fourth range including the second range and the third range as a part, and the fourth depth being deeper than the second depth and the third depth; and

providing a second heating in which the semiconductor substrate is heated so that a second p-type region is formed in a part of a region into which the p-type impurities were implanted in the fourth implantation,

wherein

the second p-type region serves as the body region, and

in the first implantation, the n-type impurities are implanted at a density higher than a density of the n-type impurities implanted in the second implantation.

3. The method of claim 2 , wherein, after the body region and the pillar region are formed, a density of the n-type impurities in the pillar region at the second depth is lower than a density of the p-type impurities in the pillar region at the first depth.

4. The method of claim 1 , wherein

the diode further comprises:

a plurality of trench gates being in contact with the body region and the barrier region;

an emitter region being of n-type, located between the trench gates, and being in contact with the trench gates and the anode electrode; and

a collector region being of p-type and located on a lower side of the barrier region, and

the contact region and the pillar region are located between the trench gates.

5. The method of claim 1 , wherein

in the first implantation, the n-type impurities are implanted through a mask having an opening, and

in the second implantation, the mask is etched so as to enlarge the opening and the n-type impurities are implanted through the mask after being etched.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: TOYOTA JIDOSHA KABUSHIKI KAISHA (AKA TOYOTA MOTOR CORPORATION)
To: DENSO CORPORATION
Reel/Frame 052280/0207 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2016
From: ONISHI, TORU; MATSUURA, YUICHIRO
To: TOYOTA JIDOSHA KABUSHIKI KAISHA
Reel/Frame 037611/0001 →
Priority Claims (1)
JP 2015-023321 · Feb 9, 2015 · national
Continuity (1)
Related Publication 20160233130A1 · Aug 11, 2016