Method and apparatus for incorporating passive devices in an integrated passive device separate from a die

1. A circuit comprising:

a first die comprising a first substrate and a plurality of active devices;

an integrated passive device comprising a first layer, a second substrate and a plurality of passive devices, wherein the second substrate comprises a plurality of vias, wherein the plurality of passive devices comprise an inductance, wherein the inductance is defined by (i) a plurality of layers of the integrated passive device including the first layer and the second substrate, and (ii) the plurality of vias, and wherein the plurality of passive devices are implemented at least on the first layer or the second substrate, and wherein a resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate; and

a second layer disposed between the first die and the integrated passive device, wherein the second layer comprises a plurality of pillars, wherein each of the plurality of pillars connects a corresponding one of the plurality of active devices to (i) one of the plurality of vias, or (ii) one of the plurality of passive devices,

wherein the first die, the integrated passive device and the second layer are disposed in a parallel arrangement relative to each other to form a stack, such that planar surfaces of the second layer are disposed between and face opposing planar surfaces of (i) the first die, and (ii) the integrated passive device, and wherein the planar surfaces are parallel to a surface of a printed circuit board on which the stack is disposed.

2. The circuit of claim 1 , further comprising:

a medium access control module configured to (i) receive data, and (ii) generate a signal comprising the data; and

a physical layer module configured to transmit the signal, wherein the physical layer module comprises the plurality of active devices and the plurality of passive devices.

3. The circuit of claim 1 , wherein the integrated passive device does not include an active device.

4. The circuit of claim 1 , wherein the plurality of active devices comprises a plurality of transistors.

5. The circuit of claim 1 , wherein:

the first die is a semiconductor die; and

the first die comprises a plurality of complementary metal-oxide semiconductor transistors.

6. The circuit of claim 1 , wherein:

the first die is a silicon-on-insulator die; and

the first die comprises a plurality of metal-oxide-semiconductor field-effect transistors.

7. The circuit of claim 1 , wherein:

the second substrate comprises glass; and

the plurality of vias comprise a through glass vias.

8. The circuit of claim 1 , wherein:

the second substrate comprises silicon; and

the plurality of vias comprise through silicon vias.

9. The circuit of claim 1 , further comprising:

a leadframe, wherein the first die is connected to the leadframe;

a first plurality of pads disposed on the leadframe;

a second plurality of pads disposed on the integrated passive device and connected to corresponding ones of the plurality of vias; and

a plurality of bond wires connecting the first plurality of pads respectively to the second plurality of pads,

wherein

the second layer is disposed on the first die, and

the integrated passive device is disposed on the second layer.

10. The circuit of claim 9 , further comprising the printed circuit board, wherein the leadframe is disposed on the printed circuit board.

11. The circuit of claim 1 , wherein:

the integrated passive device includes a first metallization layer and a second metallization layer;

the first metallization layer comprises a plurality of first conductive elements;

the second metallization layer comprises a plurality of second conductive elements;

the inductance is defined by the plurality of first conductive elements and the plurality of second conductive elements; and

at least some of the plurality of pillars are connected to corresponding ones of the plurality of vias.

12. The circuit of claim 1 , wherein the layer comprises:

interconnect devices, wherein the interconnect devices connect the plurality of vias to a plurality of solder bumps;

the second layer is disposed on a first side of the integrated passive device;

the plurality of solder bumps are on a second side of the integrated passive device opposite the first side; and

the first die is disposed on a side of the second layer opposite the integrated passive device.

13. The circuit of claim 1 , wherein:

the plurality of active devices include a first amplifier;

the first amplifier is configured to output an output signal; and

the inductance is configured to receive the output signal from the first amplifier and transmit the output signal to an antenna.

14. A circuit comprising:

a first die comprising a first substrate and a plurality of active devices, wherein the plurality of active devices include a first amplifier, and wherein the first amplifier is configured to output an output signal;

an integrated passive device comprising a first layer, a second substrate and a plurality of passive devices, wherein the second substrate comprises a plurality of vias, and wherein the plurality of passive devices include an inductance and are implemented at least on the first layer or the second substrate, wherein the inductance is configured to receive the output signal from the first amplifier and transmit the output signal to an antenna, and wherein a resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate; and

a second layer disposed between the first die and the integrated passive device, wherein the second layer comprises a plurality of pillars, wherein each of the plurality of pillars connects a corresponding one of the plurality of active devices to (i) one of the plurality of vias, or (ii) one of the plurality of passive devices,

wherein the first die, the integrated passive device and the second layer are disposed relative to each other to form a stack;

a second amplifier configured to output a second signal; and

a second inductance comprising an end,

wherein

the end of the second inductance is connected to an input of the first amplifier and to an output of the second amplifier, and

the first amplifier is configured to generate the output signal based on the second signal.

15. The circuit of claim 1 , further comprising:

a leadframe,

wherein the first die is disposed on the leadframe,

wherein the second layer is disposed on the first die, and

wherein the integrated passive device is disposed on the second layer;

a third layer disposed on the integrated passive device; and

a third substrate is disposed on the third layer, wherein the third substrate comprises a second plurality of passive devices.

16. The circuit of claim 1 , further comprising:

a third layer comprising a third substrate and a second plurality of passive devices, wherein the third layer does not comprise an active device;

the integrated passive device is disposed on the third layer; and

the second layer is disposed on the integrated passive device.

17. The circuit of claim 1 , further comprising:

a third layer disposed on the first die; and

a second die disposed on the third layer, wherein the third layer comprises a second plurality of pillars connecting the first die to the second die.

18. A method comprising:

forming a die to include a first substrate and a plurality of active devices;

forming an integrated passive device comprising a first layer, a second substrate and a plurality of passive devices, wherein the second substrate comprises a plurality of vias, wherein the plurality of passive devices comprise an inductance, wherein the inductance is defined by (i) a plurality of layers of the integrated passive device including the first layer and the second substrate, and (ii) the plurality of vias, wherein the plurality of passive devices are implemented on at least the first layer or the second substrate, and wherein a resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate; and

disposing a second layer between the die and the integrated passive device, wherein the second layer comprises a plurality of pillars, wherein the disposing of the second layer between the die and the integrated passive device includes

connecting each of the plurality of pillars to (i) a corresponding one of the plurality of active devices and to (ii) one of the plurality of vias or one of the plurality of passive devices, and

connecting at least some of the plurality of pillars to corresponding ones of the plurality of vias,

wherein the die, the integrated passive device and the second layer are disposed in a parallel arrangement relative to each other to form a stack, such that planar surfaces of the second layer are disposed between and face opposing planar surfaces of (i) the first die, and (ii) the integrated passive device, and wherein the planar surfaces are parallel to a surface of a printed circuit board on which the stack is disposed.

19. The method of claim 18 , further comprising:

connecting the die to a leadframe;

forming a first plurality of pads on the leadframe;

forming a second plurality of pads on the second layer; and

connecting the first plurality of pads to the second plurality of pads by a plurality of bond wires,

wherein

the second layer is formed on the die, and

the integrated passive device is formed on the second layer.

20. The method of claim 18 , wherein:

the second layer is formed on the integrated passive device; and

the die is stacked on the second layer.