IP Library › Granted Patent US 9,448,875
Granted Patent B2
US 9,448,875 · App. 14/098,821 · Granted Sep 20, 2016

Error recovery within integrated circuit

Inventors: Krisztian Flautner (Cambridge, GB); Todd Michael Austin (Ann Arbor, MI); David Theodore Blaauw (Ann Arbor, MI); Trevor Nigel Mudge (Ann Arbor, MI); David Bull (Cambridge, GB)
Assignees: ARM Limited; The Regents of the University of Michigan
G06F11/0793G06F11/00G06F11/0706G06F11/079G06F11/0754G06F11/1402G06F11/1604
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Quick Facts
Patent No.
US 9,448,875
App. No.
14/098,821
Granted
Sep 20, 2016
Kind
B2
Abstract

An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.

Claims (31)

1. An integrated circuit for performing data processing, said integrated circuit comprising:

an error detector configured to detect errors in operation of said integrated circuit;

error-repair circuitry configured to repair errors in operation of said integrated circuit; and

a power supply configured to apply a power supply voltage to at least one portion of said integrated circuit, wherein:

said power supply is configured to vary an error rate within said at least one portion by varying said power supply voltage to said at least one portion;

said power supply voltage to said at least one portion is provided via one or more power gates configured to vary said power supply voltage to said at least one portion; and

said power supply is controlled to produce a finite non-zero error rate within said at least one portion.

2. The integrated circuit of claim 1 , wherein said at least one portion is a power domain within said integrated circuit.

3. The integrated circuit of claim 1 , comprising power supply control circuitry configured at least to control provision of said power supply via said one or more power gates.

4. The integrated circuit of claim 2 , wherein said integrated circuit comprises a plurality of power domains with respective power supplies, said power supplies varying to vary power consumption of said integrated circuit.

5. The integrated circuit of claim 1 , wherein said power supply includes is configured to apply a body bias voltage applied to said at least one portion.

6. The integrated circuit of claim 1 , wherein at least some of said one or more power gates are controlled so as to switch off said power supply voltage supply therethrough.

7. An integrated circuit for performing data processing, said integrated circuit comprising:

error detector means for detecting errors in operation of said integrated circuit;

error-repair means for repairing errors in operation of said integrated circuit; and

a power supply configured to apply a power supply voltage to at least one portion of said integrated circuit, wherein:

said power supply is configured to vary an error rate within said at least one portion by varying said power supply voltage to said at least one portion;

said power supply voltage to said at least one portion is provided via one or more power gates configured to vary said power supply voltage to said at least one portion; and

said power supply is controlled to produce a finite non-zero error rate within said at least one portion.

8. A method of operating an integrated circuit, said method comprising the steps of:

detecting errors in operation of said integrated circuit;

repairing errors in operation of said integrated circuit; and

applying a power supply voltage to at least one portion of said integrated circuit using a power supply;

varying an error rate within said at least one portion by varying said power supply voltage applied to said at least one portion, wherein

said power supply voltage to said at least one portion is applied via one or more power gates configured to vary said power supply voltage to said at least one portion, and wherein said power supply is controlled to produce a finite non-zero error rate within said at least one portion.

9. The method of claim 8 , wherein said at least one portion is a power domain within said integrated circuit.

10. The method of claim 8 , comprising power supply control circuitry configured at least to control provision of said power supply via said one or more power gates.

11. The method of claim 9 , wherein said integrated circuit comprises a plurality of power domains with respective power supplies, said power supplies varying to vary power consumption of said integrated circuit.

12. The method of claim 8 , wherein said power supply is configured to apply a body bias voltage applied to said at least one portion.

13. The method of claim 8 , wherein at least some of said one or more power gates are controlled so as to switch off said power supply voltage therethrough.

14. The integrated circuit of claim 1 , wherein the power supply comprises a supply voltage controller.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2014
From: FLAUTNER, KRISZTIAN; BULL, DAVID
To: ARM LIMITED
Reel/Frame 032330/0958 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2014
From: AUSTIN, TODD MICHAEL; BLAAUW, DAVID THEODORE; MUDGE, TREVOR NIGEL
To: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
Reel/Frame 032330/0962 →
Continuity (8)
Continuation 12926084 · Oct 25, 2010
Continuation In Part 12461740 · Aug 21, 2009
Continuation 11636716 · Dec 11, 2006
Continuation In Part 11110961 · Apr 21, 2005
Continuation In Part 10779805 · Feb 18, 2004
Continuation In Part 10392382 · Mar 20, 2003
Provisional Application 60760399 · Jan 20, 2006
Related Publication 20140181581A1 · Jun 26, 2014