High voltage semiconductor apparatus
A vertical high voltage semiconductor apparatus includes a first conductivity semiconductor substrate; a first conductivity semiconductor layer disposed on the semiconductor substrate and having an impurity concentration lower than the semiconductor substrate; a second conductivity semiconductor layer disposed on the first conductivity semiconductor layer; a second conductivity base layer disposed on the first conductivity semiconductor layer and the second conductivity semiconductor layer and, having an impurity concentration lower than the second conductivity semiconductor layer; and a first conductivity source region selectively disposed inside the base layer. In an edge termination portion, after a region of the second conductivity semiconductor layer is removed, in the first conductivity semiconductor layer having an impurity concentration lower than that of the semiconductor substrate, second conductivity layers having a low concentration are formed such that the second conductivity layer at the innermost perimeter, the second conductivity semiconductor layer, and the base layer do not contact.
1. A high voltage semiconductor apparatus comprising:
a semiconductor substrate of a first conductivity type;
a first conductivity type semiconductor layer disposed on a front face of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate;
a second conductivity type semiconductor layer selectively disposed in a surface layer of the first conductivity type semiconductor layer;
a second conductivity type base layer having an impurity concentration lower than that of the second conductivity type semiconductor layer is disposed on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer;
a first conductivity type source region selectively disposed inside the base layer;
a first conductivity type well region penetrating the base layer from a surface of the base layer along a direction of depth and reaching the first conductivity type semiconductor layer;
a gate electrode layer between the first conductivity type source region and the first conductivity type well region, and disposed through a gate insulating film in at least a portion of an exposed portion of the surface of the base layer;
a source electrode in contact with surfaces of the first conductivity type source region and the base layer;
a drain electrode disposed on a back face of the semiconductor substrate;
a recess penetrating a portion of the base layer in an edge termination portion along a direction of depth and reaching the first conductivity type semiconductor layer; and
second conductivity type layers disposed on a surface of the first conductivity type semiconductor layer exposed on a bottom face of the recess, and each having an impurity concentration lower than that of the second conductivity type semiconductor layer, wherein
the second conductivity type layer at an innermost perimeter is disposed such that the second conductivity type layer is not in contact with the second conductivity type semiconductor layer and the base layer.
2. The high voltage semiconductor apparatus according to claim 1 , wherein
the first conductivity type semiconductor layer is an epitaxially grown layer,
the second conductivity type semiconductor layer is a diffusion layer formed using an ion implantation method,
the base layer is an epitaxially grown layer,
the first conductivity type source region is a diffusion layer formed using an ion implantation method, and
the first conductivity type well region is a diffusion layer formed using an ion implantation method.
3. The high voltage semiconductor apparatus according to claim 2 , wherein
the first conductivity type semiconductor layer, the second conductivity type semiconductor layer, and the second conductivity type base layer are made of silicon carbide.
4. The high voltage semiconductor apparatus according to claim 3 , wherein
the front face of the semiconductor substrate is a surface parallel to a surface whose crystallographic plane indices are (000-1) or a surface inclined by an angle within 10 degrees with respect thereto.
5. The high voltage semiconductor apparatus according to claim 3 , wherein
the front face of the semiconductor substrate is a surface parallel to a surface whose crystallographic plane indices are (0001) or a surface inclined by an angle within 10 degrees with respect thereto.
6. The high voltage semiconductor apparatus according to claim 1 , wherein
a distance between the second conductivity type layer at the innermost perimeter, and the second conductivity type semiconductor layer and the base layer is 20 μm or less.
7. The high voltage semiconductor apparatus according to claim 6 , wherein
the first conductivity type semiconductor layer, the second conductivity type semiconductor layer, and the second conductivity type base layer are made of silicon carbide.
8. The high voltage semiconductor apparatus according to claim 7 , wherein
the front face of the semiconductor substrate is a surface parallel to a surface whose crystallographic plane indices are (000-1) or a surface inclined by an angle within 10 degrees with respect thereto.
9. The high voltage semiconductor apparatus according to claim 7 , wherein
the front face of the semiconductor substrate is a surface parallel to a surface whose crystallographic plane indices are (0001) or a surface inclined by an angle within 10 degrees with respect thereto.
10. The high voltage semiconductor apparatus according to claim 1 , wherein
the first conductivity type semiconductor layer, the second conductivity type semiconductor layer, and the second conductivity type base layer are made of silicon carbide.
11. The high voltage semiconductor apparatus according to claim 10 , wherein
the front face of the semiconductor substrate is a surface parallel to a surface whose crystallographic plane indices are (000-1) or a surface inclined by an angle within 10 degrees with respect thereto.
12. The high voltage semiconductor apparatus according to claim 10 , wherein
the front face of the semiconductor substrate is a surface parallel to a surface whose crystallographic plane indices are (0001) or a surface inclined by an angle within 10 degrees with respect thereto.