Thin film transistor of display apparatus
Disclosed is a thin film transistor (TFT) of a display apparatus which reduces a leakage current caused by a hump and decreases screen defects. The TFT includes an active layer and a first gate electrode with a gate insulator therebetween, and a source electrode and a drain electrode respectively disposed at both ends of the active layer. The gate electrode branches as a plurality of lines and overlaps the active layer. The active layer includes one or more channel areas between the source electrode and the drain electrode, one or more dummy areas, and a plurality of link areas between the one or more channel areas to connect the one or more channel areas in one pattern. A length of each of the one or more dummy areas extends from an edge of a corresponding channel area.
1. A thin film transistor (TFT) of a display apparatus, the TFT comprising:
an active layer on a substrate;
a plurality of lines of a first gate electrode overlapping the active layer, the first gate electrode branching as a plurality of lines;
a gate insulator between the active layer and the first gate electrode; and
a source electrode and a drain electrode respectively at two ends of the active layer,
wherein the active layer comprises:
one or more channel areas between the source electrode and the drain electrode;
one or more dummy areas, a length of each of the one or more dummy areas extending from an edge of a corresponding channel area perpendicular to an operating current in the one or more channel areas; and
a plurality of link areas between the one or more channel areas to connect the one or more channel areas in one contiguous area,
wherein the one or more channel areas and the plurality of link areas are of a same layer.
2. The TFT of claim 1 , wherein a vertical width of each of the plurality of link areas is less than a vertical width of each of the plurality of lines of the first gate electrode.
3. The TFT of claim 1 , wherein a vertical width of each of the plurality of link areas is greater than a vertical width of each of the plurality of lines of the first gate electrode.
4. The TFT of claim 1 , wherein a vertical width of each of the plurality of link areas is greater than a sum of vertical widths of the plurality of lines of the first gate electrode.
5. The TFT of claim 1 , wherein each of the plurality of link areas comprises a slit, and
wherein the slit overlaps a portion corresponding to a space between the plurality of lines of the first gate electrode.
6. The TFT of claim 1 , wherein the plurality of link areas overlaps a portion corresponding to a space between the plurality of lines of the first gate electrode.
7. The TFT of claim 1 , wherein each of the one or more dummy areas protrudes from the edge of a corresponding channel area and is at an outer portion of the first gate electrode.
8. The TFT of claim 7 , wherein each of the one or more dummy areas protrudes to the outer portion of the first gate electrode by a length corresponding to a maximum of 30% of a width of the first gate electrode.
9. The TFT of claim 7 , wherein each of the one or more dummy areas protrudes to the outer portion of the first gate electrode by a length corresponding to a maximum of 30% of a width of a portion where the first gate electrode overlaps the active layer.
10. The TFT of claim 7 , wherein each of the one or more dummy areas protrudes to the outer portion of the first gate electrode by a length corresponding to a maximum of 100% of a width of a portion where the first gate electrode overlaps the active layer.
11. The TFT of claim 7 , wherein each of the one or more dummy areas protrudes from the edge or the both edges of the corresponding channel area by a length corresponding to a maximum of 30% of a horizontal width of one channel area.
12. The TFT of claim 7 , wherein an end of each of the one or more channel areas does not overlap the first gate electrode.
13. The TFT of claim 1 , wherein a first threshold voltage of each of the one or more dummy areas is higher than a second threshold voltage of each of the one or more channel areas.
14. The TFT of claim 5 , further comprising:
an insulator under the active layer; and
a second gate electrode under the insulator, the second gate electrode branching as a plurality of lines of the first gate electrode,
wherein the second gate electrode overlaps the active layer, and the first gate electrode is electrically connected to the second gate electrode.
15. The TFT of claim 14 , wherein the active layer overlaps the plurality of lines of the first gate electrode to form a multichannel on a top of the active layer.
16. The TFT of claim 14 , wherein the active layer overlaps the plurality of lines of the second gate electrode to form a multichannel on a bottom of the active layer.
17. The TFT of claim 7 , wherein an end of each of the one or more channel areas does not overlap the second gate electrode.
18. The TFT of claim 6 , further comprising:
an insulator under the active layer; and
a second gate electrode under the insulator, the second gate electrode branching as a plurality of lines of the first gate electrode,
wherein the second gate electrode overlaps the active layer, and the first gate electrode is electrically connected to the second gate electrode.
19. The TFT of claim 18 , wherein the active layer overlaps the plurality of lines of the first gate electrode to form a multichannel on a top of the active layer.
20. The TFT of claim 18 , wherein the active layer overlaps the plurality of lines of the second gate electrode to form a multichannel on a bottom of the active layer.