MEMS devices and fabrication methods thereof

1. A method comprising:

providing a micro-electro-mechanical system (MEMS) substrate having:

a shielding layer coupled to ground;

a plurality of vias coupled to the shielding layer; and

a first dielectric layer on a first side of the MEMS substrate;

providing a carrier including a plurality of cavities;

bonding the first side of the MEMS substrate on the carrier, wherein a first portion of the MEMS substrate is in direct contact with a first portion of the carrier; a second portion of the MEMS substrate is in direct contact with a second portion of the carrier; the first portion of the carrier and the second portion of the carrier are separated by a cavity; and the shielding layer fully covers a contacting surface of the first portion of the carrier and a contacting surface of the second portion of the carrier;

forming a first bonding material layer on a second side of the MEMS substrate;

applying a sacrificial layer removal process to the MEMS substrate;

providing a semiconductor substrate including a second bonding material layer; and

bonding the semiconductor substrate on the second side of the MEMS substrate.

2. The method of claim 1 , further comprising:

depositing a vapor HF stop layer on the first dielectric layer;

depositing a second dielectric layer on the vapor HF stop layer, wherein the plurality of vias are formed in the second dielectric layer; and

forming a bonding layer on the second dielectric layer.

3. The method of claim 1 , further comprising:

depositing a third dielectric layer on the carrier;

forming a plurality of openings in the carrier through an etching process;

forming a dielectric protection layer on sidewalls of the openings; and

enlarging the openings through an isotropic etching process.

4. The method of claim 1 , further comprising:

forming a plurality of MEMS openings in the MEMS substrate from the second side of the MEMS substrate;

depositing a fourth dielectric layer to fill the MEMS openings;

forming a thin conductive layer on the fourth dielectric layer;

forming the first bonding material layer on the thin conductive layer; and

patterning the thin conductive layer to form a plurality of conductive elements and movable elements.

5. The method of claim 1 , further comprising:

sealing a first side of a cavity of the carrier with a first sealing layer;

applying a thinning process to a second side of carrier until a second side of the cavity is exposed, wherein the second side of the carrier is a nonbonding side of the carrier; and

sealing the second side of the cavity with a second sealing layer.

6. The method of claim 5 , further comprising:

forming an electrical readout structure over the second side of the carrier.

7. A method comprising:

patterning a first dielectric layer on a first side of a first substrate to form a plurality of first openings in the first dielectric layer;

sealing the plurality of first openings to form a plurality of seams in the first dielectric layer;

patterning the first dielectric layer to form a plurality of second openings;

depositing a first polysilicon layer over the first dielectric layer;

patterning the first polysilicon layer to form a plurality of functional elements;

depositing a second dielectric layer over the first polysilicon layer;

forming a plurality of vias in the second dielectric layer;

depositing a bonding interface layer over the second dielectric layer, wherein the bonding interface layer is connected to a ground plane and the plurality of vias;

patterning the bonding interface layer and the second dielectric layer to form channels over the first substrate;

bonding the first substrate on a second substrate comprising cavities, wherein the bonding interface layer is in direct contact with the second substrate;

depositing a bonding material layer over a second side of the first substrate;

removing portions of the first substrate to form a plurality of openings in the first substrate;

applying an etching process to the first dielectric layer to connect the plurality of openings in the first substrate with the cavities of the second substrate; and

bonding a third substrate on the second side of the first substrate.

8. The method of claim 7 , further comprising:

depositing an oxide material over the first dielectric layer in a non-conformable manner to form overhangs at edges of the plurality of first openings.

9. The method of claim 7 , further comprising:

after the step of patterning the first dielectric layer to form the plurality of second openings, thinning the first dielectric layer to a thickness in a range from about 0.5 um to about 5 μm.

10. The method of claim 7 , wherein:

the bonding interface layer is formed of polysilicon.

11. The method of claim 7 , further comprising:

the first substrate is a MEMS substrate;

the second substrate is a carrier substrate; and

the third substrate is a CMOS substrate.

12. The method of claim 7 , further comprising:

depositing a third dielectric layer on the second substrate;

forming a plurality of openings in the second substrate through an etching process;

forming a dielectric protection layer on sidewalls of the plurality of openings; and

enlarging the plurality of openings through an isotropic etching process.

13. The method of claim 7 , wherein:

the second substrate comprises at least two cavities.

14. A method comprising:

depositing a first dielectric layer over a first side of a MEMS substrate;

forming a plurality of vias in the first dielectric layer;

depositing a bonding interface layer over the first dielectric layer, wherein the bonding interface layer is connected to a ground plane and the plurality of vias;

patterning the bonding interface layer and the first dielectric layer to form channels over the MEMS substrate;

bonding the MEMS substrate on a carrier substrate comprising cavities, wherein the bonding interface layer is in direct contact with the carrier substrate;

depositing a bonding material layer over a second side of the MEMS substrate;

removing portions of the MEMS substrate to form a plurality of openings in the MEMS substrate; and

bonding a CMOS substrate on the second side of the MEMS substrate.

15. The method of claim 14 , further comprising:

patterning a second dielectric layer on the first side of a first substrate to form a plurality of first openings in the second dielectric layer, wherein the second dielectric layer is in direct contact with the MEMS substrate;

sealing the plurality of first openings to form a plurality of seams in the second dielectric layer through an oxide deposition process;

patterning the second dielectric layer to form a plurality of second openings;

depositing a first polysilicon layer over the second dielectric layer; and

patterning the first polysilicon layer to form a plurality of functional elements.

16. The method of claim 14 , further comprising:

depositing a third dielectric layer on the carrier substrate;

forming a plurality of openings in the carrier substrate through an etching process;

forming a dielectric protection layer on sidewalls of the plurality of openings; and

enlarging the plurality of openings through an isotropic etching process.

17. The method of claim 16 , further comprising:

sealing the plurality of openings in the carrier substrate by a fourth dielectric layer;

forming a plurality of contact vias in the fourth dielectric layer; and

depositing a carrier bonding layer on the fourth dielectric layer.

18. The method of claim 14 , further comprising:

prior to the step of depositing the bonding material layer over the second side of the MEMS substrate, depositing a second polysilicon layer over the second side of the MEMS substrate.

19. The method of claim 14 , further comprising:

after step of bonding the MEMS substrate on the carrier substrate comprising cavities, thinning a non-bonding side of the carrier substrate until the cavities of the carrier substrate are exposed.

20. The method of claim 19 , further comprising:

depositing an oxide layer on the non-bonding side of the carrier substrate to seal the cavities; and

forming electrical readout structures over the oxide layer.